Proceedings of the Ninth Asian Test Symposium最新文献

Challenges for the academic test community 学术考试界面临的挑战

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.10004

M. Breuer, K. Cheng

引用次数: 0

Taiwan test industry session: value added testing in the new millennium 台湾测试产业会议:新千年的增值测试

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893594

Chung-Len Lee

{"title":"Taiwan test industry session: value added testing in the new millennium","authors":"Chung-Len Lee","doi":"10.1109/ATS.2000.893594","DOIUrl":"https://doi.org/10.1109/ATS.2000.893594","url":null,"abstract":"In the last two decades of the 20th century, the integrated circuit (IC) industry has prolonged and redefined Taiwan Economic Miracle. The relay has passed from OEM to IDM then to the foundry services. With the strong supports from the foundry and manufacturing sectors, the energetic and creative design sector has seen an unsurpassed opportunity in the new Millennium. The design sector will continue the trend and create a new horizon. The shift in the paradigm will have a significant impact on the test sector. In the Taiwan Test Industry Session, we will discuss how the test sector shall react, what the emerging technologies are, and what the new business protocol should be. We have invited distinguished members from designer, test, and ATE sectors to express their inside views. f The experts from design sectors will present their problems and requirements in the deep sub-micron circuit testing. The expert from the test sectors will present their current capability and technology roadmap regarding the technical concerns. Finally, ATE venders will showcase their advanced machine in the New Millennium to tackle the problems. Technology wise, the testing of System on Chip, System in Package, mixed signal, RF, and signal integrity are some of the issues that will be discussed. Infrastructure wise, the protocol for the technical cooperation on the test development in the circuit design stage and the model for the business operation in the final test stage are the focus of the presentations.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124393606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A waveform simulator based on Boolean process 基于布尔过程的波形模拟器

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893617

Lijian Li, Xiaoyang Yu, Cheng-Wen Wu, Y. Min

引用次数: 4

BIST TPG for SRAM cluster interconnect testing at board level 用于板级SRAM集群互连测试的BIST TPG

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893603

Chen-Huan Chiang, S. Gupta

{"title":"BIST TPG for SRAM cluster interconnect testing at board level","authors":"Chen-Huan Chiang, S. Gupta","doi":"10.1109/ATS.2000.893603","DOIUrl":"https://doi.org/10.1109/ATS.2000.893603","url":null,"abstract":"A Built-In Self-Test (BIST) methodology and a test pattern generation (TPG) architecture for testing static random access memory (SRAM) interconnect at board level via IEEE 1149.1 Boundary Scan (BS) Architecture are presented. Due to the expense and complexity of BS circuitry the widely-used SRAMs on most modern telecommunication circuit boards seldom contain BS architecture. (We call such non-boundary scan ICs cluster-ICs.) Hence, a methodology that tests the large numbers of board-level interconnects at the control, address, and data lines of cluster SRAMs is necessary. This is especially essential for board-level interconnect BIST which is used not only for manufacturing testing but also for system testing after integration. Newly identified prohibited conditions, which enable re-arrangement and merger of tests, are incorporated into test conditions for SRAM cluster interconnects. These improvements have been exploited to develop an efficient test procedure that is suitable for BIST. The proposed BIST methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable SRAM cluster interconnect faults, (iii) have low area overhead, and (iv) have short test lengths.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127251089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems 基于功能测试和故障分析的嵌入式核心系统故障覆盖增强技术

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893635

Ameet Bagwe, R. Parekhji

引用次数: 3

High speed IDDQ test and its testability for process variation 高速IDDQ测试及其工艺变化的可测试性

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893647

M. Hashizume, H. Yotsuyanagi, M. Ichimiya, T. Tamesada, M. Takeda

引用次数: 9

Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling 基于分布图的功率约束块测试调度方法与扩展树生长技术

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893668

Valentin Muresan, Xiaojun Wang, Valentin Muresan, M. Vladutiu

引用次数: 2

Testing programmable interconnect systems: an algorithmic approach 测试可编程互连系统:一种算法方法

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893642

Bin Liu, F. Lombardi, Wei-Kang Huang

引用次数: 5

Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers 测试PWM电路使用功能故障模型和紧凑的测试向量运算放大器

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893609

J. Calvano, V. Alves, M. Lubaszewski

{"title":"Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers","authors":"J. Calvano, V. Alves, M. Lubaszewski","doi":"10.1109/ATS.2000.893609","DOIUrl":"https://doi.org/10.1109/ATS.2000.893609","url":null,"abstract":"The use of analog VLSI technology on ordinary but complex electronic products has in the test one of its last frontiers. The design for testability paradigm should allow the test plan implementation early in the design cycle. However, in a successful test strategy, fault simulation should be carried out in order to evaluate appropriate test patterns, fault grade, etc. This way adequate fault models must be established. This paper shows the suitability and the straightforward consequences on testing of complex analog circuits when using OpAmp functional fault macromodels. Due to the lack of fault models, suitable for operational amplifiers fault simulation, we propose methodology for functional fault modeling and a method for test pattern generation. A fault dictionary for OpAmps is built and a procedure for compact test vector construction is proposed. The method is used to detect OpAmp faults in a pulse width modulator. The obtained results show that the proposed method is able to verify high level OpAmp requirements, such as open loop gain, slew-rate and CMMR, with good compromise between fault modeling and the analog circuit simulation complexity.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121380382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A new framework for static timing analysis, incremental timing refinement, and timing simulation 一个用于静态时序分析、增量时序优化和时序仿真的新框架

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893610

Liang-Chi Chen, S. Gupta, M. Breuer

引用次数: 16