高速IDDQ测试及其工艺变化的可测试性

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI:10.1109/ATS.2000.893647

M. Hashizume, H. Yotsuyanagi, M. Ichimiya, T. Tamesada, M. Takeda

{"title":"高速IDDQ测试及其工艺变化的可测试性","authors":"M. Hashizume, H. Yotsuyanagi, M. Ichimiya, T. Tamesada, M. Takeda","doi":"10.1109/ATS.2000.893647","DOIUrl":null,"url":null,"abstract":"A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"High speed IDDQ test and its testability for process variation\",\"authors\":\"M. Hashizume, H. Yotsuyanagi, M. Ichimiya, T. Tamesada, M. Takeda\",\"doi\":\"10.1109/ATS.2000.893647\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.\",\"PeriodicalId\":403864,\"journal\":{\"name\":\"Proceedings of the Ninth Asian Test Symposium\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-12-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Ninth Asian Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2000.893647\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Ninth Asian Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2000.893647","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 9

摘要

提出了一种新的高速IDDQ测试方法。它是基于门的负载电容的电荷电流，门的输出逻辑值通过测试输入矢量的应用从L变为H。本文针对CMOS集成电路生产过程中产生的一些工艺变化，对该测试方法的可测试性进行了检验。

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High speed IDDQ test and its testability for process variation

A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.

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Proceedings of the Ninth Asian Test Symposium

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