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Proceedings of the Ninth Asian Test Symposium最新文献

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An efficient parallel transparent diagnostic BIST 一种高效的并行透明诊断BIST
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893640
D. Huang, W. Jone
{"title":"An efficient parallel transparent diagnostic BIST","authors":"D. Huang, W. Jone","doi":"10.1109/ATS.2000.893640","DOIUrl":"https://doi.org/10.1109/ATS.2000.893640","url":null,"abstract":"In this paper, we propose a new transparent Built-in Self-Diagnosis (BISD) method to diagnose multiple embedded memory arrays with various sizes in parallel. A new transparent diagnostic interface has been proposed to perform testing in normal mode. By tolerating redundant read/write/shift operations, we develop a new march algorithm called TDiagRSMarch to achieve the goals of low hardware overhead, lower test time, and high test coverage. Experimental results demonstrate that the diagnostic efficiency of TDiagRSMarch is independent of memory topology, defect-type distribution, and degree of parallelism.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134641842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Verification of deadlock free property of high level robot control 高级机器人控制无死锁特性的验证
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893625
H. Hiraishi
{"title":"Verification of deadlock free property of high level robot control","authors":"H. Hiraishi","doi":"10.1109/ATS.2000.893625","DOIUrl":"https://doi.org/10.1109/ATS.2000.893625","url":null,"abstract":"This paper describes an efficient verification algorithm for deadlock free property of high level robot control called Task Control Architecture (TCA). TCA is a model of concurrent robot control processes. The verification tool we used is the Symbolic Model Verifier (SMV). Since the SMV is not so efficient for verification of liveness properties such as deadlock free property of many concurrent processes, we first described the deadlock free property by using safety properties that SMV can verify efficiently. In addition, we modify the symbolic model checking algorithm of the SMV so that it can handle many concurrent processes efficiently. Experimental measurements show that we can obtain more than 1000 times speed-up by these methods.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134316339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults 内存减少I/sub DDQ/测试压缩内部和外部桥接故障
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893648
T. Maeda, K. Kinoshita
{"title":"Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults","authors":"T. Maeda, K. Kinoshita","doi":"10.1109/ATS.2000.893648","DOIUrl":"https://doi.org/10.1109/ATS.2000.893648","url":null,"abstract":"I/sub DDQ/ testing is an effective method for bridging faults of CMOS circuits. Since the measurement of current in I/sub DDQ/ testing takes a long time, a short test sequence is strongly desirable for reducing test application time. In this paper we present a test compaction method for an I/sub DDQ/ test sequence using a reassignment method for all bridging faults in sequential circuits. Since a large memory space is required to treat all bridging faults, an effective fault list is required. We propose the test compaction method using an assignment list of signal values. The proposed method is realized with small size memory and runs fast for many large sequential circuits. Experimental results on the benchmark circuits show that it is effective in reducing test length for given weighted random sequences.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129541536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An efficient BIST design using LFSR-ROM architecture 采用LFSR-ROM架构的高效BIST设计
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893654
Lijian Li, Y. Min
{"title":"An efficient BIST design using LFSR-ROM architecture","authors":"Lijian Li, Y. Min","doi":"10.1109/ATS.2000.893654","DOIUrl":"https://doi.org/10.1109/ATS.2000.893654","url":null,"abstract":"Built-in self-test (BIST) is considered to be one of the most promising approaches to testing modern ICs. This paper proposes an efficient BIST design using LFSR-ROM architecture. It takes advantage of don't-care bits that remain during the process of test pattern generation. It determines the target fault set with an ATPG tool to achieve predefined fault coverage. It compresses the size of ROM in two dimensions to reduce the number of test patterns and ROM outputs as well. Experimental results demonstrate that the proposed scheme is able to reduce hardware overhead several-fold.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125201309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis 使用皮秒成像电路分析IBM G6微处理器L1缓存的非侵入式时序分析
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893614
S. Polonsky, M. McManus, D. Knebel, S. Steen, P. Sanda
{"title":"Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis","authors":"S. Polonsky, M. McManus, D. Knebel, S. Steen, P. Sanda","doi":"10.1109/ATS.2000.893614","DOIUrl":"https://doi.org/10.1109/ATS.2000.893614","url":null,"abstract":"The new non-invasive backside timing characterization technique, Picosecond Imaging Circuit Analysis (PICA), was applied to the identification and analysis of a race condition which occurred in an early design of the L1 cache of the S/390 microprocessor. The circuit switching activity was visualized in reconstructed slow motion videos of passing and failing conditions. An automated emission waveform extraction and analysis tool was used to perform a quantitative study of the failing condition.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123679055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Strong self-testability for data paths high-level synthesis 数据路径高级合成的强自测试性
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893630
Xiaowei Li, T. Masuzawa, H. Fujiwara
{"title":"Strong self-testability for data paths high-level synthesis","authors":"Xiaowei Li, T. Masuzawa, H. Fujiwara","doi":"10.1109/ATS.2000.893630","DOIUrl":"https://doi.org/10.1109/ATS.2000.893630","url":null,"abstract":"In this paper, we introduce strong self-testability for data paths at register transfer level (RTL). A high-level synthesis scheme is proposed for producing such strongly self-testable data paths. This is achieved by incorporating testability constraints during processes of register assignment and interconnection assignment. This method is based on the use of test resources reusability to improve the self-testability of data path. Experimental results are presented to demonstrate the effectiveness of the proposed approach.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126452808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On testing safety-sensitive digital systems 关于安全敏感数字系统的测试
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893670
J. Savir
{"title":"On testing safety-sensitive digital systems","authors":"J. Savir","doi":"10.1109/ATS.2000.893670","DOIUrl":"https://doi.org/10.1109/ATS.2000.893670","url":null,"abstract":"This paper deals with studying the effects of both online and off-line test during flight critical missions where safety is a major issue. The on-line test, in this context, is a test performed on a digital airborne system during some specified windows in time while it is still performing its intended task. An off-line test is a test that is performed on the digital system once it is taken off-line because of a suspected failure. Both the on-line and the off-line tests are performed during flight. The difference between the two is that the off-line test can be made more effective than the on-line test due to the longer amount of time available for testing. Moreover, the off-line test may be designed to have diagnosis and repair capabilities built-in. Upon successful repair, the faulty processor may be reconfigured back into the system. This capability will undoubtedly increase the mission reliability.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126493796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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