An efficient BIST design using LFSR-ROM architecture

Abstract

Built-in self-test (BIST) is considered to be one of the most promising approaches to testing modern ICs. This paper proposes an efficient BIST design using LFSR-ROM architecture. It takes advantage of don't-care bits that remain during the process of test pattern generation. It determines the target fault set with an ATPG tool to achieve predefined fault coverage. It compresses the size of ROM in two dimensions to reduce the number of test patterns and ROM outputs as well. Experimental results demonstrate that the proposed scheme is able to reduce hardware overhead several-fold.