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Proceedings of the Ninth Asian Test Symposium最新文献

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Cyclic greedy generation method for limited number of IDDQ tests 有限数量IDDQ测试的循环贪婪生成方法
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893650
T. Shinogi, M. Ushio, T. Hayashi
{"title":"Cyclic greedy generation method for limited number of IDDQ tests","authors":"T. Shinogi, M. Ushio, T. Hayashi","doi":"10.1109/ATS.2000.893650","DOIUrl":"https://doi.org/10.1109/ATS.2000.893650","url":null,"abstract":"This paper proposes a generation method (called Cyclic Greedy generation method) of IDDQ test sets for maximizing the number of detected faults under the constraint that the number of test patterns is limited. First this method greedily generates the given limited number of test patterns, then it greedily re-generates each pattern sequentially all over again and again in a cyclic manner. Each test pattern is generated by the iterative improvement method of random patterns. The experimental results show that the number of undetected faults remained by the Cyclic Greedy generation method is 13% less than by the pure greedy generation method in average for the large ISCAS85&89 circuits.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126441256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of memory cell array bridges on the faulty behavior in embedded DRAMs 存储单元阵列桥接对嵌入式dram故障行为的影响
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893638
Z. Al-Ars, A. V. Goor
{"title":"Impact of memory cell array bridges on the faulty behavior in embedded DRAMs","authors":"Z. Al-Ars, A. V. Goor","doi":"10.1109/ATS.2000.893638","DOIUrl":"https://doi.org/10.1109/ATS.2000.893638","url":null,"abstract":"Establishing functional faults, based on defect injection and circuit simulation, has become an important method in understanding faulty memory behavior and in improving memory tests. In this paper this approach is used to study the effects of bridges on the faulty behavior of embedded DRAM (eDRAM) devices. The paper applies the new approach of fault primitives to perform this analysis. The analysis shows the existence of previously defined memory fault models, and (re)establishes new ones. The paper also investigates the concept of dynamic faulty behavior and establishes its importance for memory devices.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121912754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Using genetic algorithms for test case generation in path testing 用遗传算法生成路径测试用例
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893632
Jin-Cherng Lin, Pu-Lin Yeh
{"title":"Using genetic algorithms for test case generation in path testing","authors":"Jin-Cherng Lin, Pu-Lin Yeh","doi":"10.1109/ATS.2000.893632","DOIUrl":"https://doi.org/10.1109/ATS.2000.893632","url":null,"abstract":"Generic algorithms are inspired by Darwin's survival of the fittest theory. This paper discusses a genetic algorithm that can automatically generate test cases to test a selected path. This algorithm takes a selected path as a target and executes sequences of operators iteratively for test cases to evolve. The evolved test case can lead the program execution to achieve the target path. A fitness function named SIMILARITY is defined to determine which test case should survive if the final test case has not been found.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127941850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Generating test items for checking illegal behaviors in software testing 生成测试项，用于检查软件测试中的非法行为
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893631
M. Hirayama, J. Okayasu, Tetsuya Yamamoto, O. Mizuno, T. Kikuno
{"title":"Generating test items for checking illegal behaviors in software testing","authors":"M. Hirayama, J. Okayasu, Tetsuya Yamamoto, O. Mizuno, T. Kikuno","doi":"10.1109/ATS.2000.893631","DOIUrl":"https://doi.org/10.1109/ATS.2000.893631","url":null,"abstract":"Even for electrical appliances, testing for illegal behaviors becomes difficult since the software system in an electrical appliance has already, become large in size. Actually the conventional method cannot generate sufficient test items for illegal behaviors. But testing illegal behaviors becomes more and more important, since the failure of electrical appliances would cause fatal effects on our daily life. We therefore propose a new method for generating appropriate test items to check illegal behaviors, which consists of the following steps: (1) describe software behavior using use case notation; (2) analyze illegal behavior by the deviation analysis technique; (3) construct a software fault tree using the above information; and (4) generate test items from the software fault tree. This paper also reports the experimental applications to actual development of an electrical appliance. The evaluation results identified that all necessary, test items for illegal behaviors are included in the resultant test items.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"362 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115947056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Functional testing of microprocessors with graded fault coverage 分级故障覆盖微处理器的功能测试
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893626
R. Kannah, C. Ravikumar
{"title":"Functional testing of microprocessors with graded fault coverage","authors":"R. Kannah, C. Ravikumar","doi":"10.1109/ATS.2000.893626","DOIUrl":"https://doi.org/10.1109/ATS.2000.893626","url":null,"abstract":"The goal of this paper is to reduce the test application time for microprocessors. Since the functional fault model is used for testing microprocessors, test development time is greatly reduced. But functional test generation leads to a large number of tests. The size of the test set is an important factor, as it determines both the storage for test instructions in the test equipment, as well as the test application time. The problem becomes still more serious when the processor is embedded as a core in a system-on-chip. Hence, in this paper we try to address the problem of reducing the number of tests. We use the available structural information about the microprocessors to drop some of the functional tests. Some valid assumptions about the faults that are present in the microprocessor, e.g., only single stuck at faults are present, is made to reduce the number of tests. We develop fault-grading concepts and use them to reduce the number of tests. We generate tests for Intel 8086, Motorola 68000 microprocessors using functional testing procedures and reduce the number of tests using our fault grader.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128863267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An FPGA-based re-configurable functional tester for memory chips 一种基于fpga的内存芯片可重构功能测试仪
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893602
Jing-Reng Huang, C. Ong, K. Cheng, Cheng-Wen Wu
{"title":"An FPGA-based re-configurable functional tester for memory chips","authors":"Jing-Reng Huang, C. Ong, K. Cheng, Cheng-Wen Wu","doi":"10.1109/ATS.2000.893602","DOIUrl":"https://doi.org/10.1109/ATS.2000.893602","url":null,"abstract":"The paper presents a prototype re-configurable tester for memory chips. The new tester consists of a memory test-circuitry compiler, a synthesis/mapping CAD tool, and an FPGA-based re-configurable hardware platform. The compiler makes user-specified parameters of memory under test (such as the address and data bus widths, the march test and the background data) as input and generates the test circuitry required to functionally, test the target memory chips. This framework not only enables the automatic synthesis/mapping of the test circuitry into the re-configurable hardware platform, it also guarantees that the hardware platform can correctly operate at the desired clock rate for the user specified parameters. The proposed solution can reduce the memory tester cost by providing hardware re-configurability to support a wide range of memory chips. We demonstrate that the prototype tester can be automatically configured to test SDRAM chips above 100 MHz.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115025914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Compaction-based test generation using state and fault information 使用状态和故障信息生成基于压缩的测试
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893619
Ashish Giani, S. Sheng, M. Hsiao, V. Agrawal
{"title":"Compaction-based test generation using state and fault information","authors":"Ashish Giani, S. Sheng, M. Hsiao, V. Agrawal","doi":"10.1109/ATS.2000.893619","DOIUrl":"https://doi.org/10.1109/ATS.2000.893619","url":null,"abstract":"Presents a new test generation procedure for sequential circuits using newly-traversed state information and newly-detected fault information obtained between successive iterations of vector compaction. Two types of technique are considered. One is based on which new states a sequential circuit is driven into, and the other is based on the new faults that are detected in the circuit between consecutive iterations of vector compaction. These data modify an otherwise random selection of vectors to bias vector sequences that cause the circuit to reach new states and cause previously undetected faults to be detected. The biased vectors, when used to extend the compacted test set, provide an intelligent selection of vectors. The extended test set is then compacted. Repeated applications of state and fault analysis, vector generation and compaction produce significantly high fault coverage using relatively small computing resources. We obtained improvements in terms of higher fault coverage, fewer vectors for the same coverage, or smaller numbers of iterations and time required, consistently for several benchmark circuits.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117322295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
TI-BIST: a temperature independent analog BIST for switched-capacitor filters TI-BIST:用于开关电容滤波器的温度无关模拟BIST
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893606
L. Carro, É. Cota, M. Lubaszewski, Y. Bertrand, F. Azaïs, M. Renovell
{"title":"TI-BIST: a temperature independent analog BIST for switched-capacitor filters","authors":"L. Carro, É. Cota, M. Lubaszewski, Y. Bertrand, F. Azaïs, M. Renovell","doi":"10.1109/ATS.2000.893606","DOIUrl":"https://doi.org/10.1109/ATS.2000.893606","url":null,"abstract":"This paper describes a method to obtain a temperature independent analog BIST. The test procedure is based on the reuse of existing analog circuits, configured either as stimuli generators or as signature analyzers. The paper explains the general problem of temperature deviation present in analog BIST, and shows an approach to overcome this limitation, validated by simulation results.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130656464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Reducing test application time for full scan circuits by the addition of transfer sequences 通过增加传输序列减少全扫描电路的测试应用时间
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893643
I. Pomeranz, S. Reddy
{"title":"Reducing test application time for full scan circuits by the addition of transfer sequences","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.2000.893643","DOIUrl":"https://doi.org/10.1109/ATS.2000.893643","url":null,"abstract":"A test set for scan designs may consist of tests where primary input vectors are embedded between a scan-in and a scan-out operation. A static compaction procedure proposed earlier reduces the test application time of such a test set by removing the scan operations at the end of one test and at the beginning of another test, and concatenating the primary input vectors of the two tests. In this work, we investigate a method to increase the number of tests that can be combined in this way, thus further reducing the number of scan operations and the test application time. This is done by inserting one or more primary input vectors between the two tests being combined. The inserted vectors help detect faults that were originally detected due to the scan operations, allowing us to combine tests that cannot be combined otherwise. We present experimental results to demonstrate that improved levels of compaction can be achieved by this method.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130154940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Test generation for fault isolation in analog circuits using behavioral models 使用行为模型的模拟电路故障隔离测试生成
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893597
S. Cherubal, A. Chatterjee
{"title":"Test generation for fault isolation in analog circuits using behavioral models","authors":"S. Cherubal, A. Chatterjee","doi":"10.1109/ATS.2000.893597","DOIUrl":"https://doi.org/10.1109/ATS.2000.893597","url":null,"abstract":"Test generation techniques to isolate failures to different parts of an analog circuit, have relied on a list of failure modes being available for the circuit being tested. This may be difficult to obtain for general analog circuits. In this paper we propose a new methodology for isolation of parametric failures in analog circuits that (a) does not require a fully specified fault list, (b) is able to work with high-level behavioral descriptions of the various sub-modules of the CUT (c) is able to isolate faults caused by multiple parameter variations in the CUT and (d) is robust in the presence of measurement noise and manufacturing tolerances of analog components. Experimental results to demonstrate the effectiveness of the proposed technique are presented.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117101813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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