Proceedings of the Ninth Asian Test Symposium最新文献_第3页

Testing domino circuits in SOI technology 测试SOI技术中的多米诺电路

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893664

E. MacDonald, N. Touba

引用次数: 1

Memory test time reduction by interconnecting test items 通过互连测试项目减少内存测试时间

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893639

Wen-Jer Wu, C. Tang

引用次数: 3

Accelerated test pattern generators for mixed-mode BIST environments 用于混合模式BIST环境的加速测试模式生成器

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893651

Wei-Lun Wang, Kuen-Jong Lee

引用次数: 2

Fault tolerant multistage interconnection networks with widely dispersed paths 具有广泛分散路径的容错多级互连网络

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893660

N. Kamiura, T. Kodera, N. Matsui

引用次数: 5

Spirit: satisfiability problem implementation for redundancy identification and test generation 精神:实现冗余识别和测试生成的可满足性问题

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893621

Emil Gizdarski, H. Fujiwara

引用次数: 5

A method for determining whether asynchronous circuits are self-checking 一种确定异步电路是否自检的方法

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893669

M. Liebelt, C. Lim

引用次数: 0

Charge sharing fault analysis and testing for CMOS domino logic circuits CMOS多米诺逻辑电路的电荷共享故障分析与测试

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893663

Ching-Hwa Cheng, W. Jone, Jinn-Shyan Wang, Shih-Chieh Chang

引用次数: 2

A testable/fault-tolerant FFT processor design 一个可测试/容错FFT处理器设计

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893661

Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu

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引用次数: 1

Design for sequential testability: an internal state reseeding approach for 100 % fault coverage 顺序可测试性设计:100%故障覆盖率的内部状态重新播种方法

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893657

M. Flottes, C. Landrault, A. Petitqueux

引用次数: 2

Peak-power reduction for multiple-scan circuits during test application 测试应用期间多扫描电路的峰值功率降低

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893666

Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen

引用次数: 73