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Proceedings of the Ninth Asian Test Symposium最新文献

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Efficient built-in self-test algorithm for memory 高效内置自检算法的内存
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893604
Sying-Jyan Wang, Chen-Jung Wei
{"title":"Efficient built-in self-test algorithm for memory","authors":"Sying-Jyan Wang, Chen-Jung Wei","doi":"10.1109/ATS.2000.893604","DOIUrl":"https://doi.org/10.1109/ATS.2000.893604","url":null,"abstract":"We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are needed for the detection of coupling faults. As a result, the number of test patterns required is less than half of the traditional method, while the extra hardware is negligible.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114421046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fsimac: a fault simulator for asynchronous sequential circuits 用于异步顺序电路的故障模拟器
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893612
S. Sur-Kolay, M. Roncken, K. Stevens, P. P. Chaudhuri, Rob Roy
{"title":"Fsimac: a fault simulator for asynchronous sequential circuits","authors":"S. Sur-Kolay, M. Roncken, K. Stevens, P. P. Chaudhuri, Rob Roy","doi":"10.1109/ATS.2000.893612","DOIUrl":"https://doi.org/10.1109/ATS.2000.893612","url":null,"abstract":"At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper presents Fsimac, a gate-level fault simulator for stuck-at and gate-delay faults in asynchronous sequential circuits. Fsimac not only evaluates combinational logic and typical asynchronous gates such as Muller C-elements, but also complex domino gates, which are widely used in high-speed designs. Our algorithm for desecting feedback loops is designed so as to minimize the iterations for simulating the unfolded circuit. We use min-max timing analysis to compute the bounds on the signal delays. Stuck-at faults are detected by comparing logic values at the primary outputs against the corresponding values in the fault-free design. For delay faults, we additionally compare min-max rime stamps for primary output signals. Fault coverage reported by Fsimac for pseudo-random tests generated by Cellular Automata show some very good results, but also indicate test holes for which more specific patterns are needed. We intend to deploy Fsimac for designing more effective CA-BIST.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127541438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Accumulation-based concurrent fault detection for linear digital state variable systems 基于累加的线性数字状态变量系统并发故障检测
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893671
I. Bayraktaroglu, A. Orailoglu
{"title":"Accumulation-based concurrent fault detection for linear digital state variable systems","authors":"I. Bayraktaroglu, A. Orailoglu","doi":"10.1109/ATS.2000.893671","DOIUrl":"https://doi.org/10.1109/ATS.2000.893671","url":null,"abstract":"An algorithmic fault detection scheme for linear digital state variable systems is proposed. The proposed scheme eliminates the necessity of observing the internal states of the system for concurrent fault detection by utilizing an accumulation-based approach. Observation merely of the inputs and the outputs results in significantly reduced area overhead and no performance penalty. Experimental results verify that 100% concurrent fault detection is attainable for linear digital state variable systems.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"29 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123509873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A high-speed IDDQ sensor implementation 一个高速IDDQ传感器的实现
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893649
Y. Antonioli, T. Inufushi, S. Nishikawa, K. Kinoshita
{"title":"A high-speed IDDQ sensor implementation","authors":"Y. Antonioli, T. Inufushi, S. Nishikawa, K. Kinoshita","doi":"10.1109/ATS.2000.893649","DOIUrl":"https://doi.org/10.1109/ATS.2000.893649","url":null,"abstract":"This paper presents an effective IDDQ sensor design implemented using a 0.35 /spl mu/m process. A straightforward feedback scheme minimizes the effect of process variations. Independent structures permit one to monitor the basic characteristics of the IDDQ sensor, i.e., resolution and speed, and to carry out a 20k-gate floppy-disk controller IDDQ test separately. Simulation and test results show accuracy better than /spl plusmn/10 /spl mu/A at 50 MHz in a 1 mA IDDQ measurement range.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131400847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
DFT and BIST techniques for the future DFT和BIST技术的未来
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893591
Hsin-Po Wang, J. Turino
{"title":"DFT and BIST techniques for the future","authors":"Hsin-Po Wang, J. Turino","doi":"10.1109/ATS.2000.893591","DOIUrl":"https://doi.org/10.1109/ATS.2000.893591","url":null,"abstract":"In this age of increasingly complex multi-million gate system-on-chip (SoC) device designs, coupled with multinational design and fabrication strategies to speed time to market for new products, new strategies are needed for insuring that new integrated circuit (IC) designs can be tested to very high levels of quality with very economical production test times.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125469629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Faster processing for microprocessor functional ATPG 更快的处理微处理器功能ATPG
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893624
J. Hirase, Shinichi Yoshimura
{"title":"Faster processing for microprocessor functional ATPG","authors":"J. Hirase, Shinichi Yoshimura","doi":"10.1109/ATS.2000.893624","DOIUrl":"https://doi.org/10.1109/ATS.2000.893624","url":null,"abstract":"In order to improve the quality of microprocessor tests, the use of instruction sets for testing is indispensable. This paper discusses how fault coverage can be improved with a short test pattern that repeatedly samples an R number of instructions as L sets from an S number of instructions and selects from amongst these L sets those for which the fault coverage can be improved. Continuing, it argues that the processing speed can be increased by selecting a certain number of sets containing an R number of instructions from an S number of instructions. This approach proved effective in tests using software created on these principles.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130547741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhanced untestable path analysis using edge graphs 增强的不可测试路径分析使用边图
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893616
S. Kajihara, T. Shimono, I. Pomeranz, S. Reddy
{"title":"Enhanced untestable path analysis using edge graphs","authors":"S. Kajihara, T. Shimono, I. Pomeranz, S. Reddy","doi":"10.1109/ATS.2000.893616","DOIUrl":"https://doi.org/10.1109/ATS.2000.893616","url":null,"abstract":"Logic circuits may have large numbers of untestable paths. Therefore, it is important for path delay fault testing to identify untestable paths prior to test generation. An earlier method, called partial path sensitization, was able to identify large numbers of untestable path delay faults by analyzing pairs of subpaths. We propose to apply this method to the edge graph of the circuit. In the edge graph, an edge corresponds to two consecutive subpaths. Thus, identification of untestable paths is done based on longer subpaths when the edge graph is used than when the original netlist is used. Experimental results presented in this paper show that the proposed method identifies more untestable paths than when the partial path sensitization method is applied to the original netlist.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121092278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Optimal test-set generation for parametric fault detection in switched capacitor filters 开关电容滤波器参数故障检测的最优测试集生成
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893605
W. Choi, R. Harjani, B. Vinnakota
{"title":"Optimal test-set generation for parametric fault detection in switched capacitor filters","authors":"W. Choi, R. Harjani, B. Vinnakota","doi":"10.1109/ATS.2000.893605","DOIUrl":"https://doi.org/10.1109/ATS.2000.893605","url":null,"abstract":"The functional performance of switched capacitor circuits is directly affected by variations in capacitor ratios. We have proposed techniques to accurately measure these capacitor ratios. In this paper we develop an optimal procedure to minimize the number of capacitor ratios that need to be measured while still maintaining the desired fault coverage. We make use of the sensitivity of individual performance specifications to specific capacitor ratios. The procedure has been validated with a number of examples including a first order lossy integrator a second order low-pass filter and sixth order high Q bandpass filter. The procedure developed in this paper can easily be extended to include other switched capacitor circuits.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134153749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An adjacency-based test pattern generator for low power BIST design 基于邻接的低功耗BIST测试图发生器
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893667
P. Girard, Loïs Guiller, C. Landrault, S. Pravossoudovitch
{"title":"An adjacency-based test pattern generator for low power BIST design","authors":"P. Girard, Loïs Guiller, C. Landrault, S. Pravossoudovitch","doi":"10.1109/ATS.2000.893667","DOIUrl":"https://doi.org/10.1109/ATS.2000.893667","url":null,"abstract":"A new BIST TPG design that is comprised of an Adjacency-based TPG plus a conventional pseudo-random TPG (i.e. a LFSR) is presented in this paper. When used to generate test patterns for test-per-clock BIST, it reduces the number of transitions that occur in the CUT and hence decreases the average and peak power consumption during testing. Moreover, the total energy consumption during BIST is also reduced since the test length produced by the mixed TPG is roughly the same as the test length produced by a classical LFSR-based TPG to reach the same fault coverage. Note that this TPG design has been developed to deal with strongly connected circuits with a small number of inputs.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"2000 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128270455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Test sequence compaction for sequential circuits with reset states 具有复位状态的顺序电路的测试序列压缩
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893620
Y. Higami, Y. Takamatsu, K. Kinoshita
{"title":"Test sequence compaction for sequential circuits with reset states","authors":"Y. Higami, Y. Takamatsu, K. Kinoshita","doi":"10.1109/ATS.2000.893620","DOIUrl":"https://doi.org/10.1109/ATS.2000.893620","url":null,"abstract":"Proposes a static test compaction method for sequential circuits with reset states under a single stuck-at fault assumption. The proposed method first finds unremovable vectors by fault-dropping fault simulation or by non-fault-dropping fault simulation. Next, a subset of test vectors other than unremovable vectors are replaced with a reset signal. Detection of faults detected by an original test sequence is guaranteed by logic simulation and fault simulation for test subsequences. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132742796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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