具有复位状态的顺序电路的测试序列压缩

Y. Higami, Y. Takamatsu, K. Kinoshita
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引用次数: 3

摘要

提出了一种在单卡故障假设下具有复位状态的顺序电路的静态测试压缩方法。该方法首先通过降错故障模拟或非降错故障模拟找到不可去除的向量。接下来,除不可移动向量外的测试向量子集被重置信号替换。通过逻辑仿真和测试子序列故障仿真,保证了原始测试序列检测到的故障的检测。基准电路的实验结果证明了该方法的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Test sequence compaction for sequential circuits with reset states
Proposes a static test compaction method for sequential circuits with reset states under a single stuck-at fault assumption. The proposed method first finds unremovable vectors by fault-dropping fault simulation or by non-fault-dropping fault simulation. Next, a subset of test vectors other than unremovable vectors are replaced with a reset signal. Detection of faults detected by an original test sequence is guaranteed by logic simulation and fault simulation for test subsequences. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method.
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