{"title":"DFT和BIST技术的未来","authors":"Hsin-Po Wang, J. Turino","doi":"10.1109/ATS.2000.893591","DOIUrl":null,"url":null,"abstract":"In this age of increasingly complex multi-million gate system-on-chip (SoC) device designs, coupled with multinational design and fabrication strategies to speed time to market for new products, new strategies are needed for insuring that new integrated circuit (IC) designs can be tested to very high levels of quality with very economical production test times.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"DFT and BIST techniques for the future\",\"authors\":\"Hsin-Po Wang, J. Turino\",\"doi\":\"10.1109/ATS.2000.893591\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this age of increasingly complex multi-million gate system-on-chip (SoC) device designs, coupled with multinational design and fabrication strategies to speed time to market for new products, new strategies are needed for insuring that new integrated circuit (IC) designs can be tested to very high levels of quality with very economical production test times.\",\"PeriodicalId\":403864,\"journal\":{\"name\":\"Proceedings of the Ninth Asian Test Symposium\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-12-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Ninth Asian Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2000.893591\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Ninth Asian Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2000.893591","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this age of increasingly complex multi-million gate system-on-chip (SoC) device designs, coupled with multinational design and fabrication strategies to speed time to market for new products, new strategies are needed for insuring that new integrated circuit (IC) designs can be tested to very high levels of quality with very economical production test times.
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