Proceedings of the Ninth Asian Test Symposium最新文献_第5页

Embedded core testing using genetic algorithms 使用遗传算法的嵌入式核心测试

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893634

Ruofan Xu, M. Hsiao

引用次数: 8

Effective parallel processing techniques for the generation of test data for a logic built-in self test system 逻辑内置自测系统测试数据生成的有效并行处理技术

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893652

Paul Chang, B. Keller, S. Paliwal

{"title":"Effective parallel processing techniques for the generation of test data for a logic built-in self test system","authors":"Paul Chang, B. Keller, S. Paliwal","doi":"10.1109/ATS.2000.893652","DOIUrl":"https://doi.org/10.1109/ATS.2000.893652","url":null,"abstract":"Logic Built-in Self rest (LBIST) is a test methodology adopted by some companies to test their complex processor designs. It can involve a very high volume of simulation, perhaps up to one to two million patterns. For large designs, the simulation time (which includes logic simulation, random stimulus generation and signature computations) can be enormous. Parallel processing provides a relief for this long simulation time. This paper describes a technique to efficiently partition patterns among different processors. These patterns are derived from on-product Pseudo-Random Pattern Generators (PRPGs) and the signature is a serial compression of the response data from all of the patterns. Both the PRPG and signature calculation have a serial pattern dependency, which normally would prohibit parallel simulation of the patterns. We show how to quickly advance a PRPG state to jump ahead to any specific pattern's starting state and an innovative post processing technique to compute correct signatures from initially incorrect ones computed in parallel among different processes. The results demonstrate that the overhead to correct the signatures is small and the parallel speed up is very effective.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121759608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

High-speed generation of LFSR signatures 高速生成LFSR签名

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893629

Ming-Der Shieh, Hsin-Fu Lo, M. Sheu

引用次数: 2

Testing in the fourth dimension 在第四维进行测试

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893589

V. Agrawal, K. Cheng

引用次数: 0

On the feasibility of fault simulation using partial circuit descriptions 论用局部电路描述进行故障仿真的可行性

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893611

I. Pomeranz, S. Reddy

引用次数: 0

Testing approach within FPGA-based fault tolerant systems 基于fpga的容错系统测试方法

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893658

A. Doumar, Hideo Ito

{"title":"Testing approach within FPGA-based fault tolerant systems","authors":"A. Doumar, Hideo Ito","doi":"10.1109/ATS.2000.893658","DOIUrl":"https://doi.org/10.1109/ATS.2000.893658","url":null,"abstract":"Proposes a test strategy for FPGAs to be applied within FPGA-based fault-tolerant systems. We propose to make some configurable logic blocks (CLBs) under test and to implement the rest of the CLBs with the normal user data. In the target fault-tolerant systems, there are two phases (the functional phase and the test phase). In the functional phase, the system achieves its normal functionality, while in the test phase, the FPGA is tested. In this phase, the configuration data of the CLBs under test are shifted on-chip in parallel to other CLBs for achieving the test in these CLBs. All the CLBs are tested in a single test phase. The shifting process control, test application and test observation are achieved by the logic managing the fault tolerance (from outside the chip). The system returns to its normal phase after all the CLBs have been scanned by the test. The application of this approach reduces the fault tolerance cost (hardware, software, time, etc). The user is then able to periodically test the chip using only the data inside the chip and without destroying the original configuration data. No particular hardware is required for saving the test data on-board. Additionally, no particular software treatment is required for the test. The testing time is reduced enormously. Unfortunately, as a consequence of implementing two types of data on-chip, a 15% decrease in the chip functionality and a 2.5% delay overhead are noticed in the case of structures similar to a 20/spl times/20 Xilinx FPGA.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130036918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

DFT closure DFT关闭

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893592

F. Hayat, T. Williams, R. Kapur, D. Hsu

引用次数: 5

A BIST methodology for at-speed testing of data communications transceivers 数据通信收发器高速测试的BIST方法

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893628

S. Lin, S. Mourad, S. Krishnan

引用次数: 2

On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction DO-RE-ME/MPG-D相对于基于卡滞的缺陷件水平预测的优越性

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893618

Jennifer Dworak, M. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. R. Mercer

引用次数: 8

Novel techniques for improving testability analysis 改进可测试性分析的新技术

Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893655

Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang

{"title":"Novel techniques for improving testability analysis","authors":"Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang","doi":"10.1109/ATS.2000.893655","DOIUrl":"https://doi.org/10.1109/ATS.2000.893655","url":null,"abstract":"The purpose of a testability analysis program is to estimate the difficulty of testing a fault. A good measurement can give an early warning about the testing problem so as to provide guidance in improving the testability of a circuit. There have been researches attempting to efficiently compute the testability analysis. Among those, the Controllability and Observability Procedure COP (1984) can calculate the testability value of a stuck-at fault efficiently in a tree-structured circuit but may be very inaccurate for a general circuit. The inaccuracy in COP is due to the ignorance of signal correlations. The algorithm of TAIR (Testability Analysis by Implication Reasoning) proposes a testability analysis algorithm, which starts from the result of COP and then gradually improves the result by applying a set of rules. The set of rules in TAIR can capture some signal correlations and therefore the results of TAIR are more accurate than COP. In this paper, we first prove that the rules in TAIR can be replaced by a closed-form formulation. Then, based on the closed-form formulation, we proposed two novel techniques to further improve the testability analysis results. Our experimental results have shown improvement over the results of TAIR.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115492593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4