{"title":"数据通信收发器高速测试的BIST方法","authors":"S. Lin, S. Mourad, S. Krishnan","doi":"10.1109/ATS.2000.893628","DOIUrl":null,"url":null,"abstract":"This paper discusses a new BIST methodology suitable for functional testing of transceivers on a data communications chip. Practical circuits are presented which allow the at-speed resting of various functional blocks. The concept has been applied to test a 400 Mbps 3-port IEEE 1394a system. The silicon for the 0.35 /spl mu/m CMOS implementation is expected in early 2001.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A BIST methodology for at-speed testing of data communications transceivers\",\"authors\":\"S. Lin, S. Mourad, S. Krishnan\",\"doi\":\"10.1109/ATS.2000.893628\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses a new BIST methodology suitable for functional testing of transceivers on a data communications chip. Practical circuits are presented which allow the at-speed resting of various functional blocks. The concept has been applied to test a 400 Mbps 3-port IEEE 1394a system. The silicon for the 0.35 /spl mu/m CMOS implementation is expected in early 2001.\",\"PeriodicalId\":403864,\"journal\":{\"name\":\"Proceedings of the Ninth Asian Test Symposium\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-12-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Ninth Asian Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2000.893628\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Ninth Asian Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2000.893628","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A BIST methodology for at-speed testing of data communications transceivers
This paper discusses a new BIST methodology suitable for functional testing of transceivers on a data communications chip. Practical circuits are presented which allow the at-speed resting of various functional blocks. The concept has been applied to test a 400 Mbps 3-port IEEE 1394a system. The silicon for the 0.35 /spl mu/m CMOS implementation is expected in early 2001.
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