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Proceedings of the Ninth Asian Test Symposium最新文献

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Novel techniques for improving testability analysis 改进可测试性分析的新技术
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893655
Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang
{"title":"Novel techniques for improving testability analysis","authors":"Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang","doi":"10.1109/ATS.2000.893655","DOIUrl":"https://doi.org/10.1109/ATS.2000.893655","url":null,"abstract":"The purpose of a testability analysis program is to estimate the difficulty of testing a fault. A good measurement can give an early warning about the testing problem so as to provide guidance in improving the testability of a circuit. There have been researches attempting to efficiently compute the testability analysis. Among those, the Controllability and Observability Procedure COP (1984) can calculate the testability value of a stuck-at fault efficiently in a tree-structured circuit but may be very inaccurate for a general circuit. The inaccuracy in COP is due to the ignorance of signal correlations. The algorithm of TAIR (Testability Analysis by Implication Reasoning) proposes a testability analysis algorithm, which starts from the result of COP and then gradually improves the result by applying a set of rules. The set of rules in TAIR can capture some signal correlations and therefore the results of TAIR are more accurate than COP. In this paper, we first prove that the rules in TAIR can be replaced by a closed-form formulation. Then, based on the closed-form formulation, we proposed two novel techniques to further improve the testability analysis results. Our experimental results have shown improvement over the results of TAIR.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115492593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Single-control testability of RTL data paths for BIST BIST RTL数据路径的单控制可测试性
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893627
T. Masuzawa, Minoru Izutsu, H. Wada, H. Fujiwara
{"title":"Single-control testability of RTL data paths for BIST","authors":"T. Masuzawa, Minoru Izutsu, H. Wada, H. Fujiwara","doi":"10.1109/ATS.2000.893627","DOIUrl":"https://doi.org/10.1109/ATS.2000.893627","url":null,"abstract":"This paper presents a new BIST method for RTL data paths based on single-control testability a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses, paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single stuck-at faults), low hardware overhead and capability of at-speed testing. Moreover test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at the speed of the system clock.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"33 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120877225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits 模拟电阻式桥接故障，以尽量减少CMOS电路中压和振荡的存在
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893613
A. Keshk, Y. Miura, K. Kinoshita
{"title":"Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits","authors":"A. Keshk, Y. Miura, K. Kinoshita","doi":"10.1109/ATS.2000.893613","DOIUrl":"https://doi.org/10.1109/ATS.2000.893613","url":null,"abstract":"This paper presents an efficient procedure to improve logic testing for bridging faults (BF) in CMOS circuits. A unified procedure is presented that extracts the test vector from transistor level networks, which will reduce the occurrence of intermediate voltage that leads to Byzantine General's problems and feedback oscillation. By using this procedure according to fault location, the fault coverage of logic testing will increase without using both simulation and a complex calculation for predicting bridging voltage or logic threshold of the driven gates.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121961183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Collaboration between industry and academia in test research 工业界和学术界在测试研究方面的合作
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.10002
K. Cheng, V. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
{"title":"Collaboration between industry and academia in test research","authors":"K. Cheng, V. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu","doi":"10.1109/ATS.2000.10002","DOIUrl":"https://doi.org/10.1109/ATS.2000.10002","url":null,"abstract":"Even though there is a great need for innovative advances and excellen. research opportunities in test and diagnosis, various issues faced by academic and industrial test researchers seem to make it harder to perform research that could create wide impact to the industry. Diversifying technologies, limited access to design and manufacturing data, increasing cost for building required infrastructure for experiments with reasonable scale, application-specific nature of test solutions, etc. are among those often cited issues. The panel will discuss how academia and industry have contributed to test technology in the past, evaluate the current health of academic and industrial test research and explore how academia and industry can collaborate to meet the challenges in test and to increase its impact to the industry. Specifically, the panel will discuss the following topics: What collaboration models between university and industry in the test area are mosdleast successful? What are the emerging research topics that academic or industrial research is ill equipped to make real contributions? Will promoting the academic test research to “get real”, “get practical”, and “work closely with industry”, adversely discourage high risk, “long term” basic research and pursuing major breakthroughs?","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125907831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Forecasting the efficiency of test generation algorithms for digital circuits 预测数字电路测试生成算法的效率
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893622
Shiyi Xu, Wei Cen
{"title":"Forecasting the efficiency of test generation algorithms for digital circuits","authors":"Shiyi Xu, Wei Cen","doi":"10.1109/ATS.2000.893622","DOIUrl":"https://doi.org/10.1109/ATS.2000.893622","url":null,"abstract":"Within this era of VLSI circuits, testability is truly a very crucial issue. To generate a test set for a given circuit (including both combinational and sequential circuits), choice of an algorithm within a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. In this paper, the genetic algorithms are used to construct the models of existing test generation algorithms in making such choice more easily. Therefore, we may forecast the testability parameters of a circuit before using the real test generation algorithm. The results also can be used to evaluate the efficiency of the existing test generation algorithms. Experimental results are given to confirm the validity and usefulness of this approach.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130905229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A built-in self-test and self-diagnosis scheme for embedded SRAM 嵌入式SRAM的内置自检和自诊断方案
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893601
Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
{"title":"A built-in self-test and self-diagnosis scheme for embedded SRAM","authors":"Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin","doi":"10.1109/ATS.2000.893601","DOIUrl":"https://doi.org/10.1109/ATS.2000.893601","url":null,"abstract":"Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133479933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 62
Current status and future trend on CAD tools for VLSI testing 超大规模集成电路测试CAD工具的现状及未来趋势
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893593
Wu-Tung Cheng
{"title":"Current status and future trend on CAD tools for VLSI testing","authors":"Wu-Tung Cheng","doi":"10.1109/ATS.2000.893593","DOIUrl":"https://doi.org/10.1109/ATS.2000.893593","url":null,"abstract":"For current VLSI designs, there are two kinds of well-accepted digital testing technologies. One is for embedded memories and the other is for the logic. For embedded memories, Built-In-Self-Test (BIST) is used. For the logic, the main solutions are based on scan DFT and automatic test pattern generation (ATPG). However, to reduce the need to use an external tester, and to ease test reuse at the system level, more designs are using BIST to test logic. In the future, with system on chip (SoC) requirements and deep Sub-Micron (DSM) technologies, we believe that BIST and scan-based ATPG will continue to be the main solutions to VLSI testing. However, to be successful, some improvements are needed. The author discusses future trends in three categories: test quality, test application cost and test development effort.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128464977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata 基于一维线性混合元胞自动机的快速、低成本串行播种TPGs的设计与测试
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893653
A. Hlawiczka, M. Kopec
{"title":"Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata","authors":"A. Hlawiczka, M. Kopec","doi":"10.1109/ATS.2000.893653","DOIUrl":"https://doi.org/10.1109/ATS.2000.893653","url":null,"abstract":"The paper proposes the approach of designing CA registers that work as quick pattern generators. A new effective method of setting the initial state of such registers is presented. It is based on switching a n-cell CA register into a concatenation of p CdSR registers (Cellular Automata quasi Shift Register) each containing r cells and connected with characteristic polynomial x'. The resultant characteristic polynomial of such concatenation is p(x)=x/sup n/. Such concatenation of p registers CASR is referred as PCASR. The paper proves the possibility of setting a PCASR to any initial state by n-bit input sequence without the need of switching flip-flops into the D flip-flop mode. Moreover, it has been proven that any input sequence would be repeated at the output of a n-cell PCASR after n-clock cycle delay. Finally an effective procedure of testing PCASR is proposed.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122463968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Is IDDQ testing not applicable for deep submicron VLSI in year 2011? IDDQ测试在2011年不适用于深亚微米VLSI吗?
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893646
Chih-Wen Lu, C. Su, Chung-Len Lee, Jwu-E Chen
{"title":"Is IDDQ testing not applicable for deep submicron VLSI in year 2011?","authors":"Chih-Wen Lu, C. Su, Chung-Len Lee, Jwu-E Chen","doi":"10.1109/ATS.2000.893646","DOIUrl":"https://doi.org/10.1109/ATS.2000.893646","url":null,"abstract":"In this work, IDDQ current for deep submicron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1/spl times/10/sup 7/ gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep submicron VLSI for the next ten years.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114335763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A methodology for fault model development for hierarchical linear systems 层次线性系统的故障模型开发方法
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893608
Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu-E Chen, C. Su
{"title":"A methodology for fault model development for hierarchical linear systems","authors":"Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu-E Chen, C. Su","doi":"10.1109/ATS.2000.893608","DOIUrl":"https://doi.org/10.1109/ATS.2000.893608","url":null,"abstract":"In this paper, a methodology to develop fault models for hierarchical linear systems which are composed of operational amplifiers (OP) is demonstrated and presented. The methodology at first presents a transfer function model for the open-loop OP based on analysis of element faults at the transistor level. Then it derives a transfer function model for the closed loop OP based on the derived open-loop OP level model, again a higher level fault model for a module which is composed of closed loop OPs. The models can handle ac faults. The benchmark state-variable filter is used as an example to demonstrate for this methodology. An application of the derived models to Monte Carlo simulation to save computation time is also demonstrated.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114726496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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