Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits

A. Keshk, Y. Miura, K. Kinoshita
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引用次数: 1

Abstract

This paper presents an efficient procedure to improve logic testing for bridging faults (BF) in CMOS circuits. A unified procedure is presented that extracts the test vector from transistor level networks, which will reduce the occurrence of intermediate voltage that leads to Byzantine General's problems and feedback oscillation. By using this procedure according to fault location, the fault coverage of logic testing will increase without using both simulation and a complex calculation for predicting bridging voltage or logic threshold of the driven gates.
模拟电阻式桥接故障,以尽量减少CMOS电路中压和振荡的存在
本文提出了一种改进CMOS电路桥接故障逻辑测试的有效方法。提出了一种从晶体管级网络中提取测试矢量的统一方法,减少了中间电压的出现,从而减少了拜占庭将军问题和反馈振荡。根据故障定位采用该程序,可以提高逻辑测试的故障覆盖率,而无需进行仿真和复杂的计算来预测桥接电压或驱动门的逻辑阈值。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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