A testable/fault-tolerant FFT processor design

Abstract

With the advent of VLSI technology, a large collection of processing elements can be gathered to achieve high-speed computation economically. However, due to the low pin-count-to-component-count ratio, the controllability and observability of such circuits decrease significantly. As a result, the testing of such highly complex and dense circuits becomes very difficult and expensive. A testable/fault-tolerant FFT processor is proposed in this paper. We first propose a testable design scheme for FFT butterfly networks based on M-testability conditions. According to the M-testability conditions, a novel design-for-testability approach is presented and applied to the module-level systolic FFT arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. Based on this testable design, a reconfiguration mechanism is incorporated to bypass the faulty cells and the testable/fault-tolerant structures are constructed. Special cell designs are presented to implement the design-for-testability and reconfiguration mechanisms. The reliability of the FFT system increases significantly and the hardware overhead is low-about 16% for the module-level design.