Functional testing of microprocessors with graded fault coverage

Abstract

The goal of this paper is to reduce the test application time for microprocessors. Since the functional fault model is used for testing microprocessors, test development time is greatly reduced. But functional test generation leads to a large number of tests. The size of the test set is an important factor, as it determines both the storage for test instructions in the test equipment, as well as the test application time. The problem becomes still more serious when the processor is embedded as a core in a system-on-chip. Hence, in this paper we try to address the problem of reducing the number of tests. We use the available structural information about the microprocessors to drop some of the functional tests. Some valid assumptions about the faults that are present in the microprocessor, e.g., only single stuck at faults are present, is made to reduce the number of tests. We develop fault-grading concepts and use them to reduce the number of tests. We generate tests for Intel 8086, Motorola 68000 microprocessors using functional testing procedures and reduce the number of tests using our fault grader.