A hierarchical test control architecture for core based design

Abstract

Recently system-on-chip (SOC) design based on IP cores has become the trend of IC design. To prevent the testing problem from becoming the bottleneck of the core-based design, the IEEE P1500 Working Group is defining a test standard that can greatly simplify the core test problem. In this paper, we propose a new core-based test architecture that can support the IEEE P1500 cores as well as the well-accepted IEEE 1149.1 cores. Both the serial and parallel testing capabilities are provided. Moreover, a new hierarchical test control mechanism has been developed that facilitates the hierarchical test access for deeply embedded cores.