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2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)最新文献

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Verifying the accuracy of 2x-Thru de-embedding for unsymmetrical test fixtures 验证非对称测试夹具的2x-Thru去嵌入精度
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329760
H. Barnes, J. Moreira
{"title":"Verifying the accuracy of 2x-Thru de-embedding for unsymmetrical test fixtures","authors":"H. Barnes, J. Moreira","doi":"10.1109/EPEPS.2017.8329760","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329760","url":null,"abstract":"Due to its simplicity, the 2x-Thru test fixture de-embedding algorithm has been gaining acceptance by the test and measurement community. One common misconception of the 2x-Thru de-embedding algorithm is that it requires the test fixture to be symmetric on both sides of the DUT. To handle an unsymmetrical test fixture design, one can simply implement a separate 2x-Thru structure for each of the fixtures connecting to the DUT and thus, separate the problem into two symmetrical 2x-Thru structures. In this paper, we will leverage a kit of PCB test structures with coaxial adapters to validate the accuracy of 2x-Thru de-embedding algorithms for unsymmetrical test fixtures.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128307669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Toward virtual prototyping of power electronics: Model order reduction for tight-coupled electro-thermal simulation 面向电力电子的虚拟样机:紧耦合电热仿真的模型阶数缩减
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329741
N. Wong, Quan Chen
{"title":"Toward virtual prototyping of power electronics: Model order reduction for tight-coupled electro-thermal simulation","authors":"N. Wong, Quan Chen","doi":"10.1109/EPEPS.2017.8329741","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329741","url":null,"abstract":"This work describes a nonlinear projection-based model order reduction (MOR) method specialized for tightly-coupled transient electro-thermal (ET) simulation of power electronic modules, one attempt to enable multi-domain virtual prototyping for power electronics design. The MOR scheme is applied directly on the field-based ET system of equations. The main feature lies in the separation of weak and strong nonlinearities present in the problem, with the former being directly reduced and the latter treated as external inputs. This treatment ensures the efficiency of projection-based MOR by maintaining a small number of inputs and enables Newton's type of solution of the reduced nonlinear system leading to faster convergence.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128332318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A parallel iterative layered-medium integral-equation solver for electromagnetic analysis of electronic packages 电子封装电磁分析的平行迭代分层介质积分方程求解器
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329759
C. Liu, K. Aygün, H. Braunisch, V. Okhmatovski, A. Yılmaz
{"title":"A parallel iterative layered-medium integral-equation solver for electromagnetic analysis of electronic packages","authors":"C. Liu, K. Aygün, H. Braunisch, V. Okhmatovski, A. Yılmaz","doi":"10.1109/EPEPS.2017.8329759","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329759","url":null,"abstract":"A parallel iterative solver for multiport network parameter extraction of large-scale electronic packages is presented. The proposed solver is based on a frequency-domain integral-equation formulation that accounts for the substrate using planar layered-medium Green's functions, conductor loss/ roughness using an impedance boundary condition, and port truncations using a non-radiating lumped port model. The parallel iterative solution is accelerated by a sparse preconditioner and an FFT-based matrix-vector multiplication algorithm. A scalability study demonstrates the solver's suitability for analyzing high-fidelity and large-scale package models.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129337264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Stitching impedance analysis of LPDDR power plane split and its impact to radio frequency interference (RFI) and signal integrity (SI) LPDDR功率平面劈裂的拼接阻抗分析及其对射频干扰和信号完整性的影响
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329745
Ying-Ern Ho, Hao-han Hsu, Jun Liao, X. Cai
{"title":"Stitching impedance analysis of LPDDR power plane split and its impact to radio frequency interference (RFI) and signal integrity (SI)","authors":"Ying-Ern Ho, Hao-han Hsu, Jun Liao, X. Cai","doi":"10.1109/EPEPS.2017.8329745","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329745","url":null,"abstract":"This paper presents low-power double data rate 5 (LPDDR5) power plane stitching impedance impact to radio frequency interference (RFI) and Signal Integrity (SI). LPDDR5 power plane split causes RFI and SI degradation, but can be mitigated through appropriate power plane stitching impedance. It is found that stitching capacitor's impedance needs to be less than 10 ohm to minimize RFI and SI degradation. With stitching impedance as low as 0.5 ohm, (a) RFI is suppressed by ∼20dB, (b) near end and far end crosstalk (NEXT and FEXT) are reduced by ∼45mV, while (c) eye height (EH) and eye width (EW) improved by 57mV and 31ps respectively. These findings are helpful in improving radio performance of the system and increasing the LPDDR memory speed bin of mobile device.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131366192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Distributed sinusoidal resonant converter with high step-down ratio 高降压比分布正弦谐振变换器
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329708
Kan Xu, Boris Vaisband, G. Sizikov, Xin Li, E. Friedman
{"title":"Distributed sinusoidal resonant converter with high step-down ratio","authors":"Kan Xu, Boris Vaisband, G. Sizikov, Xin Li, E. Friedman","doi":"10.1109/EPEPS.2017.8329708","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329708","url":null,"abstract":"A novel zero-current switching transformer-based sinusoidal resonant converter topology for point-of-load DC-DC conversion is presented in this paper. A sinusoidal resonant converter within a distributed power system, where high step-down ratios are required, is challenging due to the large parasitic impedance seen by the primary stage. A sinusoidal resonant converter with a distributed topology is introduced here to reduce the transformer turns ratio while maintaining a high step-down ratio. A power efficiency of 89.8% is achieved. The proposed distributed converter is highly scalable and exhibits sinusoidal current and voltage waveforms with low current spikes. Application to systems-in-package, wireless devices, and IoT is expected due to the low EMI and high efficiency characteristics of this distributed converter system.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134643528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Improve mm-wave measurement repeatability and accuracy by increasing coaxial connector pin gap 通过增加同轴连接器引脚间隙，提高毫米波测量的重复性和精度
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329732
Ken Wong, J. Hoffmann
{"title":"Improve mm-wave measurement repeatability and accuracy by increasing coaxial connector pin gap","authors":"Ken Wong, J. Hoffmann","doi":"10.1109/EPEPS.2017.8329732","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329732","url":null,"abstract":"For decades, we were taught that connector pin gap must be kept to a minimum to reduce reflection and hence improve device performance and measurement accuracy. Yet, measurement inconsistencies were observed between calibration methods, such as sliding load, TRL and offset short, especially at frequencies above 18 GHz. Measurement repeatability was another frustrating experience for practitioners of high precision measurements, such as TRL calibration. The root cause of these measurement inconsistencies wasn't identified until recently. The \"connector and gap effect\" was discovered and finally these measurement inconsistencies can be explained with an appropriate model. This paper will review the observed measurement issues, present the theoretical base of the connector effect and show how measurement accuracy can be improved.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"68 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114011366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DC blocking capacitor interfacing for high speed communication buses 用于高速通信总线的直流阻塞电容接口
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329752
Junyan Tang, J. Hejase, M. Richardson, D. Dreps, W. Becker, Y. Kwark, J. Audet, C. Baks
{"title":"DC blocking capacitor interfacing for high speed communication buses","authors":"Junyan Tang, J. Hejase, M. Richardson, D. Dreps, W. Becker, Y. Kwark, J. Audet, C. Baks","doi":"10.1109/EPEPS.2017.8329752","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329752","url":null,"abstract":"This paper studies integration aspects of DC blocking capacitors in differential high speed bus channels. The presence of a DC blocking capacitor in the signal path can present an impedance mismatched medium which can lead to signal degradation. Integrating the capacitor to minimize impedance mismatches becomes of high importance. The differential impedance of a micro-strip differential pair is evaluated in simulation under different physical design conditions. Additionally, test vehicle measurements for a variety of capacitor test sites with different characteristics including: package size, voiding scenarios under capacitor pads/packages and wiring layers for traces to the capacitors has been designed and fabricated. The test sites are measured up to 20GHz using a VNA and their results are discussed. Also, several of the test sites are simulated in order to validate the modelling method for future design analysis purposes.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121858359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Full-wave electromagnetic characterization of 3D interconnects using a surface integral formulation 使用曲面积分公式的三维互连的全波电磁特性
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329738
U. Patel, Shashwat Sharma, Shunchuan Yang, S. Hum, P. Triverio
{"title":"Full-wave electromagnetic characterization of 3D interconnects using a surface integral formulation","authors":"U. Patel, Shashwat Sharma, Shunchuan Yang, S. Hum, P. Triverio","doi":"10.1109/EPEPS.2017.8329738","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329738","url":null,"abstract":"This paper presents an accurate surface integral equation formulation for modeling interconnects. It accurately captures the skin effect inside conductors using a recently-developed 3D differential surface admittance operator. Numerical results demonstrate that the proposed formulation is significantly more efficient than existing volumetric techniques in terms of computational time and memory consumption.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124983017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Field-circuit coextraction of systems with interconnects and circuit components 带有互连器件和电路元件的系统的现场电路提取
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329713
Jian Liu, Kaiyu Mao, Xiande Cao, Yingxin Sun, Anyu Kuo
{"title":"Field-circuit coextraction of systems with interconnects and circuit components","authors":"Jian Liu, Kaiyu Mao, Xiande Cao, Yingxin Sun, Anyu Kuo","doi":"10.1109/EPEPS.2017.8329713","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329713","url":null,"abstract":"A field-circuit coextraction method is proposed for the 3D full-wave model extraction of systems with interconnects and surface mounting circuit components. Local metal patches are added to each circuit component based on the pins and circuit profile. The voltage and the current continuity between fields and circuits are enforced through internal ports defined on the artificial reference patches.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126907923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new approach to mitigate PCI express Gen4 crosstalk from sideband signals in connectors 一种缓解连接器边带信号中PCI express Gen4串扰的新方法
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI: 10.1109/EPEPS.2017.8329754
Yaping Zhou, Wenjun Shi, Sunil R. Sudhakaran
{"title":"A new approach to mitigate PCI express Gen4 crosstalk from sideband signals in connectors","authors":"Yaping Zhou, Wenjun Shi, Sunil R. Sudhakaran","doi":"10.1109/EPEPS.2017.8329754","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329754","url":null,"abstract":"RC termination for sideband signals is required in PCIe Gen4 Card Electromechanical specification to reduce crosstalk in PCIe connectors. A new approach to reduce crosstalk is proposed in this paper. This approach doesn't require extra components, and simulation results show that the new proposal can achieve even better electrical performance.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"59 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126077360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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