{"title":"Verifying the accuracy of 2x-Thru de-embedding for unsymmetrical test fixtures","authors":"H. Barnes, J. Moreira","doi":"10.1109/EPEPS.2017.8329760","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329760","url":null,"abstract":"Due to its simplicity, the 2x-Thru test fixture de-embedding algorithm has been gaining acceptance by the test and measurement community. One common misconception of the 2x-Thru de-embedding algorithm is that it requires the test fixture to be symmetric on both sides of the DUT. To handle an unsymmetrical test fixture design, one can simply implement a separate 2x-Thru structure for each of the fixtures connecting to the DUT and thus, separate the problem into two symmetrical 2x-Thru structures. In this paper, we will leverage a kit of PCB test structures with coaxial adapters to validate the accuracy of 2x-Thru de-embedding algorithms for unsymmetrical test fixtures.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128307669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Toward virtual prototyping of power electronics: Model order reduction for tight-coupled electro-thermal simulation","authors":"N. Wong, Quan Chen","doi":"10.1109/EPEPS.2017.8329741","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329741","url":null,"abstract":"This work describes a nonlinear projection-based model order reduction (MOR) method specialized for tightly-coupled transient electro-thermal (ET) simulation of power electronic modules, one attempt to enable multi-domain virtual prototyping for power electronics design. The MOR scheme is applied directly on the field-based ET system of equations. The main feature lies in the separation of weak and strong nonlinearities present in the problem, with the former being directly reduced and the latter treated as external inputs. This treatment ensures the efficiency of projection-based MOR by maintaining a small number of inputs and enables Newton's type of solution of the reduced nonlinear system leading to faster convergence.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128332318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Liu, K. Aygün, H. Braunisch, V. Okhmatovski, A. Yılmaz
{"title":"A parallel iterative layered-medium integral-equation solver for electromagnetic analysis of electronic packages","authors":"C. Liu, K. Aygün, H. Braunisch, V. Okhmatovski, A. Yılmaz","doi":"10.1109/EPEPS.2017.8329759","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329759","url":null,"abstract":"A parallel iterative solver for multiport network parameter extraction of large-scale electronic packages is presented. The proposed solver is based on a frequency-domain integral-equation formulation that accounts for the substrate using planar layered-medium Green's functions, conductor loss/ roughness using an impedance boundary condition, and port truncations using a non-radiating lumped port model. The parallel iterative solution is accelerated by a sparse preconditioner and an FFT-based matrix-vector multiplication algorithm. A scalability study demonstrates the solver's suitability for analyzing high-fidelity and large-scale package models.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129337264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Stitching impedance analysis of LPDDR power plane split and its impact to radio frequency interference (RFI) and signal integrity (SI)","authors":"Ying-Ern Ho, Hao-han Hsu, Jun Liao, X. Cai","doi":"10.1109/EPEPS.2017.8329745","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329745","url":null,"abstract":"This paper presents low-power double data rate 5 (LPDDR5) power plane stitching impedance impact to radio frequency interference (RFI) and Signal Integrity (SI). LPDDR5 power plane split causes RFI and SI degradation, but can be mitigated through appropriate power plane stitching impedance. It is found that stitching capacitor's impedance needs to be less than 10 ohm to minimize RFI and SI degradation. With stitching impedance as low as 0.5 ohm, (a) RFI is suppressed by ∼20dB, (b) near end and far end crosstalk (NEXT and FEXT) are reduced by ∼45mV, while (c) eye height (EH) and eye width (EW) improved by 57mV and 31ps respectively. These findings are helpful in improving radio performance of the system and increasing the LPDDR memory speed bin of mobile device.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131366192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kan Xu, Boris Vaisband, G. Sizikov, Xin Li, E. Friedman
{"title":"Distributed sinusoidal resonant converter with high step-down ratio","authors":"Kan Xu, Boris Vaisband, G. Sizikov, Xin Li, E. Friedman","doi":"10.1109/EPEPS.2017.8329708","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329708","url":null,"abstract":"A novel zero-current switching transformer-based sinusoidal resonant converter topology for point-of-load DC-DC conversion is presented in this paper. A sinusoidal resonant converter within a distributed power system, where high step-down ratios are required, is challenging due to the large parasitic impedance seen by the primary stage. A sinusoidal resonant converter with a distributed topology is introduced here to reduce the transformer turns ratio while maintaining a high step-down ratio. A power efficiency of 89.8% is achieved. The proposed distributed converter is highly scalable and exhibits sinusoidal current and voltage waveforms with low current spikes. Application to systems-in-package, wireless devices, and IoT is expected due to the low EMI and high efficiency characteristics of this distributed converter system.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134643528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
U. Patel, Shashwat Sharma, Shunchuan Yang, S. Hum, P. Triverio
{"title":"Full-wave electromagnetic characterization of 3D interconnects using a surface integral formulation","authors":"U. Patel, Shashwat Sharma, Shunchuan Yang, S. Hum, P. Triverio","doi":"10.1109/EPEPS.2017.8329738","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329738","url":null,"abstract":"This paper presents an accurate surface integral equation formulation for modeling interconnects. It accurately captures the skin effect inside conductors using a recently-developed 3D differential surface admittance operator. Numerical results demonstrate that the proposed formulation is significantly more efficient than existing volumetric techniques in terms of computational time and memory consumption.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124983017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improve mm-wave measurement repeatability and accuracy by increasing coaxial connector pin gap","authors":"Ken Wong, J. Hoffmann","doi":"10.1109/EPEPS.2017.8329732","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329732","url":null,"abstract":"For decades, we were taught that connector pin gap must be kept to a minimum to reduce reflection and hence improve device performance and measurement accuracy. Yet, measurement inconsistencies were observed between calibration methods, such as sliding load, TRL and offset short, especially at frequencies above 18 GHz. Measurement repeatability was another frustrating experience for practitioners of high precision measurements, such as TRL calibration. The root cause of these measurement inconsistencies wasn't identified until recently. The \"connector and gap effect\" was discovered and finally these measurement inconsistencies can be explained with an appropriate model. This paper will review the observed measurement issues, present the theoretical base of the connector effect and show how measurement accuracy can be improved.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"68 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114011366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Unified approach to interconnect conductor surface roughness modelling","authors":"Y. Shlepnev","doi":"10.1109/epeps.2017.8329704","DOIUrl":"https://doi.org/10.1109/epeps.2017.8329704","url":null,"abstract":"Commonalities of five conductor roughness models are analysed and unified form of roughness correction coefficient (RCC) is suggested in the paper. It is shown that Hammerstad, Huray, Groiss, Hemispherical and Bushminskiy roughness correction coefficients can be written in the following unified form K=1+(RF-1)∗F(SR), where RF is roughness factor that has meaning of maximal possible increase of losses with frequency due to the conductor roughness. F is a frequency-dependent function describing transition from zero at lower frequencies to one at higher frequencies (roughness transition function). It is shown that the unified RCC can be used in multi-level additive form for surfaces with two or more dominant discontinuity sizes or in multi-level multiplicative form for surfaces with fractal type discontinuities. Measurements on a test board are used to identify and compare all five RCCs.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"35 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116536852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Boosting off-chip interconnects through chip-to-chip capacitive coupled communication","authors":"Xiang Zhang, Dongwon Park, Chung-Kuan Cheng","doi":"10.1109/EPEPS.2017.8329736","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329736","url":null,"abstract":"We propose Chip-to-Chip Capacitive Coupled Communication (5C) to increase off-chip communication through the metal plate on the side wall of the chip packaging, as the chip to chip spacing for the state of the art electronic designs has been reduced due to the advances of design for manufacturing (DFM) technologies. We demonstrate 5C can transmit 20Gbps data on each channel and provide noise immunity to the coupling noise from adjacent channel.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123759742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Discontinuous Galerkin time-domain analysis of power/ground plate pairs with wave port excitation","authors":"Ping Li, L. J. Jiang, H. Bağcı","doi":"10.1109/EPEPS.2017.8329717","DOIUrl":"https://doi.org/10.1109/EPEPS.2017.8329717","url":null,"abstract":"In this work, a discontinuous Galerkin time-domain method is developed to analyze the power/ground plate pairs taking into account arbitrarily shaped antipads. To implement proper source excitations over the antipads, the magnetic surface current expanded by the electric eigen-modes supported by the corresponding antipad is employed as the excitation. For irregularly shaped antipads, the eigen-modes are obtained by numerical approach. Accordingly, the methodology for the S-parameter extraction is derived based on the orthogonal properties of the different modes. Based on the approach, the transformation between different modes can be readily evaluated.","PeriodicalId":397179,"journal":{"name":"2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128366231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}