Stitching impedance analysis of LPDDR power plane split and its impact to radio frequency interference (RFI) and signal integrity (SI)

Ying-Ern Ho, Hao-han Hsu, Jun Liao, X. Cai
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引用次数: 2

Abstract

This paper presents low-power double data rate 5 (LPDDR5) power plane stitching impedance impact to radio frequency interference (RFI) and Signal Integrity (SI). LPDDR5 power plane split causes RFI and SI degradation, but can be mitigated through appropriate power plane stitching impedance. It is found that stitching capacitor's impedance needs to be less than 10 ohm to minimize RFI and SI degradation. With stitching impedance as low as 0.5 ohm, (a) RFI is suppressed by ∼20dB, (b) near end and far end crosstalk (NEXT and FEXT) are reduced by ∼45mV, while (c) eye height (EH) and eye width (EW) improved by 57mV and 31ps respectively. These findings are helpful in improving radio performance of the system and increasing the LPDDR memory speed bin of mobile device.
LPDDR功率平面劈裂的拼接阻抗分析及其对射频干扰和信号完整性的影响
研究了低功率双数据速率5 (LPDDR5)功率平面拼接阻抗对射频干扰(RFI)和信号完整性(SI)的影响。LPDDR5功率平面分裂导致RFI和SI退化,但可以通过适当的功率平面拼接阻抗来缓解。研究发现,拼接电容的阻抗需要小于10欧姆,以减少RFI和SI的退化。当拼接阻抗低至0.5 ohm时,(a) RFI被抑制了~ 20dB, (b)近端和远端串扰(NEXT和ext)降低了~ 45mV, (c)眼高(EH)和眼宽(EW)分别提高了57mV和31ps。这些研究结果对于提高系统的无线电性能和提高移动设备的LPDDR存储速度具有重要意义。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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