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8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings最新文献

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Optimizing the vertical IGBT structure-the NPT concept as the most economic and electrically ideal solution for a 1200 V-IGBT 优化垂直IGBT结构——NPT概念是1200 V-IGBT最经济、最理想的电气解决方案
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509473
T. Laska, J. Fugger, F. Hirler, W. Scholz
{"title":"Optimizing the vertical IGBT structure-the NPT concept as the most economic and electrically ideal solution for a 1200 V-IGBT","authors":"T. Laska, J. Fugger, F. Hirler, W. Scholz","doi":"10.1109/ISPSD.1996.509473","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509473","url":null,"abstract":"In this paper a new low loss 1200 V IGBT is discussed: optimizing the vertical structure of a fast switching IGBT in economic standard NPT-DMOS-technology, will result (without increase of switching losses) in a lowered on state voltage close to 2 V, a value which until now was believed to be reachable only by implementing problematic trench technology. Key points in this development are improvements in the ability of handling thin wafers below 200 /spl mu/m as well as modifications of the backside p emitter.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115715836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
High voltage LDMOS transistors in sub-micron SOI films 亚微米SOI薄膜中的高压LDMOS晶体管
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509455
K. Paul, Y. Leung, J. Plummer, S.S. Wong, S. Kuehne, V. Huang, C. Nguyen
{"title":"High voltage LDMOS transistors in sub-micron SOI films","authors":"K. Paul, Y. Leung, J. Plummer, S.S. Wong, S. Kuehne, V. Huang, C. Nguyen","doi":"10.1109/ISPSD.1996.509455","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509455","url":null,"abstract":"Silicon-on-insulator (SOI) LDMOS transistors with a linearly graded doping profile in the drift region have been found to exhibit both low on-resistance and high breakdown voltage. High-side operation is a problem for devices built in very thin SOI layers due to pinch-off of the drift region. This is less of a problem for devices built in thicker SOI layers. Devices built in thicker SOI films also are more tolerant of manufacturing variations and offer more predictable behaviour. Non-uniform self-heating within the drift region has been measured for the first time. A breakdown voltage of 1020 V is reported for a LDMOS transistor made in a 0.15 /spl mu/m SOI layer.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126366428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Future trends in local lifetime control [power semiconductor devices] 局部寿命控制的未来趋势[功率半导体器件]
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509471
J. Vobecký, P. Hazdra
{"title":"Future trends in local lifetime control [power semiconductor devices]","authors":"J. Vobecký, P. Hazdra","doi":"10.1109/ISPSD.1996.509471","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509471","url":null,"abstract":"Energy and dose mixing concept, applied in ion irradiation technology for local lifetime tailoring, is shown to be capable of creating a customer-specific lifetime profile. The electrical parameters of power diode, subjected to the new ion irradiation concept, are compared with those ones resulting from the energy dispersed alpha particle irradiation.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121564297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A critical look at the performance advantages and limitations of 4H-SiC power UMOSFET structures 对4H-SiC功率UMOSFET结构的性能优势和局限性的批判性观察
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509462
A. Agarwal, R. Siergiej, S. Seshadri, M. White, P. McMullin, A. Burk, L. Rowland, C. Brandt, R. Hopkins
{"title":"A critical look at the performance advantages and limitations of 4H-SiC power UMOSFET structures","authors":"A. Agarwal, R. Siergiej, S. Seshadri, M. White, P. McMullin, A. Burk, L. Rowland, C. Brandt, R. Hopkins","doi":"10.1109/ISPSD.1996.509462","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509462","url":null,"abstract":"A realistic performance projection of 4H-SiC UMOSFET structures based on electric field in the gate insulator consistent with long-term reliability of insulator is provided for the breakdown voltage in the range of 600 to 1500 V. The use of P/sup +/ polysilicon gate leads to higher breakdown voltage as the Fowler Nordheim injection from the gate electrode is reduced. It is concluded that the insulator reliability is the limiting factor and therefore the high temperature operation of these devices may not be practical.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131614420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A fully resurfed, BiCMOS-compatible, high voltage MOS transistor 一个完全充电，bicmos兼容，高压MOS晶体管
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509467
Min Liu, C. Salama, P. Schvan, M. King
{"title":"A fully resurfed, BiCMOS-compatible, high voltage MOS transistor","authors":"Min Liu, C. Salama, P. Schvan, M. King","doi":"10.1109/ISPSD.1996.509467","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509467","url":null,"abstract":"In this paper a fully resurfed, high voltage MOS structure compatible with submicron BiCMOS technology is proposed and implemented. The device is junction-isolated and is therefore suitable for high-side drive applications. Using this structure, the resurf condition in the device can be optimized without altering the well regions. Devices with breakdown voltages over 200 V and specific on-resistances on the order of 20 m/spl Omega//spl middot/cm/sup 2/ were obtained.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132131019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 30-V P-channel trench gated DMOSFET with 900 /spl mu//spl Omega/-cm/sup 2/ specific on-resistance at 2.7 V 一个30v p沟道门控DMOSFET，在2.7 V时具有900 /spl mu//spl Omega/-cm/sup 2/比导通电阻
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509447
R.K. Williams, W. Grabowski, M. Darwish, H. Yilmaz, M. Chang, K. Owyang
{"title":"A 30-V P-channel trench gated DMOSFET with 900 /spl mu//spl Omega/-cm/sup 2/ specific on-resistance at 2.7 V","authors":"R.K. Williams, W. Grabowski, M. Darwish, H. Yilmaz, M. Chang, K. Owyang","doi":"10.1109/ISPSD.1996.509447","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509447","url":null,"abstract":"A scaled-oxide low-threshold P-channel trench gated DMOS employing a 12 Mcell/in/sup 2/. (2 Mcell/cm/sup 2/) closed-cell design, 8-V gate rating and 30-V drain rating is described. Measured specific resistances of 900 /spl mu//spl Omega/-cm/sup 2/ at V/sub G/S=2.7 V and 700 /spl mu//spl Omega/-cm/sup 2/. At V/sub GS/=4.5 V represent the lowest R/sub DSA/ values ever reported for a P-channel DMOS with a 37-V breakdown. The benefit of a 3X scaling of gate oxide thickness is shown by measurement, analytical and numerical modeling to produce a 1.6-V reduction in threshold, a 75% reduction in channel resistance and a 45% reduction in overall trench DMOS on-resistance at V/sub GS/=4.5 V. High density 30-V planar DMOS die resistance is shown to be 3.7X that of the scaled-oxide trench DMOS at V/sub GS/=4.5 V.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116812368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Optimization of LIGBTs in a dielectric insulated IC-technology using a 'switched anode' 使用“开关阳极”的介电绝缘集成电路技术中光源的优化
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509490
K. Oppermann, M. Stoisiek
{"title":"Optimization of LIGBTs in a dielectric insulated IC-technology using a 'switched anode'","authors":"K. Oppermann, M. Stoisiek","doi":"10.1109/ISPSD.1996.509490","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509490","url":null,"abstract":"The design of an IGBT is always a compromise between a low on state voltage drop and low switching losses. MOS-controlled emitter shorts are well known as a means to overcome this compromise but previous solutions suffer from parasitic effects and restrictions in the optimization of the high voltage part and the emitter shorting MOSFET. In this paper we propose for the first time an LIGBT where the MOSFET for shorting the p/sup +/-emitter is not merged within the high voltage structure but realized as a separated device integrated on the same chip. It is experimentally shown how with the gate voltage of the bypass MOSFET the composed device can be switched between a MOSFET mode and an IGBT mode, how by proper timing of the control voltage the turn off energy can be reduced to one third, and how it is possible to use the internal p-base/n-substrate diode of the LIGBT.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122092359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An intelligent power MOSFET with reverse battery protection for automotive applications 一种智能功率MOSFET，具有反向电池保护，适用于汽车应用
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509448
K. Sakamoto, N. Fuchigami, K. Takagawa, S. Ohtaka
{"title":"An intelligent power MOSFET with reverse battery protection for automotive applications","authors":"K. Sakamoto, N. Fuchigami, K. Takagawa, S. Ohtaka","doi":"10.1109/ISPSD.1996.509448","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509448","url":null,"abstract":"An intelligent power MOSFET with built-in reverse battery protection, which is essential for automotive power switches, has been developed. The reverse battery protection is achieved without using external control signals. This new power MOSFET can replace the conventional three-terminal power MOSFETs used in automotive applications. Its positive drain breakdown voltage is 71 V and the negative drain current at a drain voltage of -16 V is only -750 /spl mu/A. On resistance is 170 m/spl Omega/. Using the latest fabrication process now available for commercial products, the on-resistance can be reduced to less than 50 m /spl Omega/ in a TO-220 package.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128778164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An observation of large and long current pulses below the breakdown voltage of PIN diode PIN二极管击穿电压以下大且长电流脉冲的观察
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509476
I. Takata
{"title":"An observation of large and long current pulses below the breakdown voltage of PIN diode","authors":"I. Takata","doi":"10.1109/ISPSD.1996.509476","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509476","url":null,"abstract":"PIN diodes with high resistive n-layer exhibit very interesting pulses, whose lengths are 10 /spl mu/s-2 s and heights are 0.001/spl sim/0.25 A/cm/sup 2/ below and above the avalanche breakdown voltage (/spl ap/1400 V). Especially, large pulses (0.1/spl sim/0.25 A/cm/sup 2/) occurred at /spl ap/100 V lower voltage than the avalanche breakdown. In these operations, breakdown currents prefer some discrete values not depending on the applied voltage directly. To consider these phenomena, the author proposes a new idea that there was a stable high current density operation (1A/cm/sup 2/ order) near the avalanche breakdown voltage.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131761587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
2.5 kV-1000 A power pack IGBT (high power flat-packaged RC-IGBT) 2.5 kV-1000 A电源组IGBT(大功率平板封装RC-IGBT)
8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI: 10.1109/ISPSD.1996.509502
Y. Takahashi, K. Yoshikawa, M. Soutome, T. Fujii, M. Ichijyou, Y. Seki
{"title":"2.5 kV-1000 A power pack IGBT (high power flat-packaged RC-IGBT)","authors":"Y. Takahashi, K. Yoshikawa, M. Soutome, T. Fujii, M. Ichijyou, Y. Seki","doi":"10.1109/ISPSD.1996.509502","DOIUrl":"https://doi.org/10.1109/ISPSD.1996.509502","url":null,"abstract":"A 2.5 kV-1000 A Power Pack IGBT has been successfully developed. This Power Pack IGBT is specially designed for the high power and highly reliable industrial and traction use. Compared with conventional IGBT modules, this Power Pack IGBT is simple and compact for a 2.5 kV-1 kA class device because the assembled IGBT and PWD chips are able to shrink due to the low thermal impedance of both side cooling. The Power Pack IGBT shows the high blocking voltage of 2.5 kV, the maximum on-state voltage of 4.5 V at the collector current I/sub c/=1000 A, T/sub j/=125/spl deg/C, and the turn-off capability of over 5/spl times/I/sub c/.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123557631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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