一个30v p沟道门控DMOSFET，在2.7 V时具有900 /spl mu//spl Omega/-cm/sup 2/比导通电阻

8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings Pub Date : 1996-05-20 DOI:10.1109/ISPSD.1996.509447

R.K. Williams, W. Grabowski, M. Darwish, H. Yilmaz, M. Chang, K. Owyang

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引用次数: 6

摘要

一种采用12 Mcell/in/sup 2/的氧化鳞片低阈值p沟槽门控DMOS。(2 mccell /cm/sup 2/)闭孔设计，8 v栅极额定值和30 v漏极额定值。测量的比电阻为900 /spl mu//spl Omega/-cm/sup 2/ V/sub G/S=2.7 V和700 /spl mu//spl Omega/-cm/sup 2/。在V/sub时，GS/=4.5 V表示具有37 V击穿的p通道DMOS的最低R/sub DSA/值。测量、分析和数值模拟表明，栅极氧化物厚度缩放3倍的好处是，在V/sub GS/=4.5 V时，阈值降低1.6 V，沟道电阻降低75%，沟道DMOS总导通电阻降低45%。在V/sub /=4.5 V时，高密度平面DMOS的电阻是氧化沟槽DMOS的3.7倍。

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A 30-V P-channel trench gated DMOSFET with 900 /spl mu//spl Omega/-cm/sup 2/ specific on-resistance at 2.7 V

A scaled-oxide low-threshold P-channel trench gated DMOS employing a 12 Mcell/in/sup 2/. (2 Mcell/cm/sup 2/) closed-cell design, 8-V gate rating and 30-V drain rating is described. Measured specific resistances of 900 /spl mu//spl Omega/-cm/sup 2/ at V/sub G/S=2.7 V and 700 /spl mu//spl Omega/-cm/sup 2/. At V/sub GS/=4.5 V represent the lowest R/sub DSA/ values ever reported for a P-channel DMOS with a 37-V breakdown. The benefit of a 3X scaling of gate oxide thickness is shown by measurement, analytical and numerical modeling to produce a 1.6-V reduction in threshold, a 75% reduction in channel resistance and a 45% reduction in overall trench DMOS on-resistance at V/sub GS/=4.5 V. High density 30-V planar DMOS die resistance is shown to be 3.7X that of the scaled-oxide trench DMOS at V/sub GS/=4.5 V.

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8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings

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