亚微米SOI薄膜中的高压LDMOS晶体管

K. Paul, Y. Leung, J. Plummer, S.S. Wong, S. Kuehne, V. Huang, C. Nguyen
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引用次数: 25

摘要

在漂移区线性梯度掺杂的绝缘体上硅(SOI) LDMOS晶体管具有低导通电阻和高击穿电压。由于漂移区域的掐断,对于在非常薄的SOI层中构建的器件来说,高侧操作是一个问题。对于内置在较厚的SOI层中的设备来说,这不是一个问题。用更厚的SOI薄膜制造的设备也更能容忍制造变化,并提供更可预测的行为。首次在漂移区测量了非均匀自热。据报道,在0.15 /spl mu/m SOI层中制造的LDMOS晶体管击穿电压为1020 V。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High voltage LDMOS transistors in sub-micron SOI films
Silicon-on-insulator (SOI) LDMOS transistors with a linearly graded doping profile in the drift region have been found to exhibit both low on-resistance and high breakdown voltage. High-side operation is a problem for devices built in very thin SOI layers due to pinch-off of the drift region. This is less of a problem for devices built in thicker SOI layers. Devices built in thicker SOI films also are more tolerant of manufacturing variations and offer more predictable behaviour. Non-uniform self-heating within the drift region has been measured for the first time. A breakdown voltage of 1020 V is reported for a LDMOS transistor made in a 0.15 /spl mu/m SOI layer.
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