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International Semiconductor Device Research Symposium, 2003最新文献

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Calculation of lattice heating in 4H-SiC RF power devices, based on 2D electrical and 3D thermal simulations 基于二维电学和三维热模拟的4H-SiC射频功率器件晶格加热计算
International Semiconductor Device Research Symposium, 2003 Pub Date : 2003-12-10 DOI: 10.1109/ISDRS.2003.1272140
K. Bertilsson, C. Harris, H. Nilsson
{"title":"Calculation of lattice heating in 4H-SiC RF power devices, based on 2D electrical and 3D thermal simulations","authors":"K. Bertilsson, C. Harris, H. Nilsson","doi":"10.1109/ISDRS.2003.1272140","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272140","url":null,"abstract":"The paper presents the thermal effects of 4H-SiC RF power devices using simulation based on a combination of 2D device simulations for the electrical transport and 3D thermal simulation for the lattice heating. Using the combined device simulation model the feasibility for different kinds of layouts and the influence on the device performance for SiC RF power MESFET is presented.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128215079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new dual-material double-gate (DMDG) SOI MOSFET for nanoscale CMOS design 用于纳米级CMOS设计的新型双材料双栅(DMDG) SOI MOSFET
International Semiconductor Device Research Symposium, 2003 Pub Date : 2003-12-10 DOI: 10.1109/ISDRS.2003.1272078
G. Reddy, M.J. Kumar
{"title":"A new dual-material double-gate (DMDG) SOI MOSFET for nanoscale CMOS design","authors":"G. Reddy, M.J. Kumar","doi":"10.1109/ISDRS.2003.1272078","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272078","url":null,"abstract":"Double-gate (DG) SOI MOSFETs employing asymmetrical gate structure (front gate p/sup +/ poly and back gate n/sup +/ poly) are foreseen to be a solution to the scaling limits imposed by bulk MOSFETs. However, for channel lengths below 100 nm, the DG SOI MOSFET is not completely immune to the short-channel effects and in the main challenge in device design. In this paper a new dual-material double-gate (DMDG) SOI MOSFET to overcome this nanoscale regime while simultaneously achieving a higher transconductance and reduced drain induced barrier lowering compared to the DG SOI MOSFET is proposed using two-dimensional simulations. This article further demonstrates a considerable reduction in the peak electric field near the drain end, increased drain breakdown voltage and the desirable threshold voltage \"roll-up\" even for channel lengths far below 100 nm. The DMDG structure exhibits a step function in the surface potential along the channel. The I/sub D/-V/sub DS/ characteristics of both the devices are discussed.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131238943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Integratable SiGe phototransistor with high speed (BW=3 GHz) and extremely-high avalanche responsivity 具有高速(BW=3 GHz)和极高雪崩响应度的可积SiGe光电晶体管
International Semiconductor Device Research Symposium, 2003 Pub Date : 2003-12-10 DOI: 10.1109/ISDRS.2003.1271975
Z. Pei, J. Shi, Y. Hsu, F. Yuan, C. Liang, C. Liu, T. Pan, S. Lu, W. Hsieh, M. Tsai
{"title":"Integratable SiGe phototransistor with high speed (BW=3 GHz) and extremely-high avalanche responsivity","authors":"Z. Pei, J. Shi, Y. Hsu, F. Yuan, C. Liang, C. Liu, T. Pan, S. Lu, W. Hsieh, M. Tsai","doi":"10.1109/ISDRS.2003.1271975","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1271975","url":null,"abstract":"In this paper, we discuss about the SiGe phototransistors (HPT) with SiGe/Si multiple quantum well (MQW) absorption layers and integratable SiGe phototransistor with high speed (BW=3 GHz) and extremely-high avalanche responsivity have been demonstrated. The properly designed non-ideal (nkT) base current can increase the speed of HPT, and have an avalanche bias with extremely high gain. The bandwidth of 3 GHz at normal bias is obtained with transistor's f/sub T/ of /spl sim/ 70 GHz. The integrated photoreceiver using commercial SiGe/Si HBT foundry is feasible.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134126665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The field effect diode 场效应二极管
International Semiconductor Device Research Symposium, 2003 Pub Date : 2003-12-10 DOI: 10.1109/ISDRS.2003.1272077
F. Taghibakhsh
{"title":"The field effect diode","authors":"F. Taghibakhsh","doi":"10.1109/ISDRS.2003.1272077","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272077","url":null,"abstract":"The fabrication of field effect diode (FED) as a planar pin diode with two gates over its intrinsic region using SOI technology is presented in this paper. The voltage applied to the gates, changes the barrier height against carriers and therefore modulates diode current. Based on an accurate numeric simulation, the operation of the device has been explained, the analytical I-V relationship has been extracted, dynamic characteristics of the device has been calculated and the effect of device parameters on its electrical behavior has been studied. Obtained results show that the FED realizes a voltage controlled voltage source.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134346916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Single-electron turnstile using Si-wire charge-coupled devices 使用硅丝电荷耦合器件的单电子旋转门
International Semiconductor Device Research Symposium, 2003 Pub Date : 2003-12-10 DOI: 10.1109/ISDRS.2003.1272208
A. Fujiwara, N. Zimmerman, Y. Ono, Y. Takahashi
{"title":"Single-electron turnstile using Si-wire charge-coupled devices","authors":"A. Fujiwara, N. Zimmerman, Y. Ono, Y. Takahashi","doi":"10.1109/ISDRS.2003.1272208","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272208","url":null,"abstract":"This paper reports a quantized current in a Si-wire charge-coupled device (CCD), which simply consists of a Si-wire channel with gates. Based on a simple gate-voltage control of tunnel barriers, current plateaus were observed successfully at 20 K with frequencies up to 100 MHz. SEM observations were made for the fabricated device, it shows that the charge island is mainly coupled to the upper and wide gate.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"85 25","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113944233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and fabrication of Schottky diode, on-chip RF power detector 肖特基二极管、片上射频功率检测器的设计与制造
International Semiconductor Device Research Symposium, 2003 Pub Date : 2003-12-10 DOI: 10.1109/ISDRS.2003.1272103
W. Jeon, John C. Rodgers, J. Melngailis
{"title":"Design and fabrication of Schottky diode, on-chip RF power detector","authors":"W. Jeon, John C. Rodgers, J. Melngailis","doi":"10.1109/ISDRS.2003.1272103","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272103","url":null,"abstract":"Schottky diodes are fast rectifying devices and can be used as RF power detectors. In this article we designed a mask set for fabricating Schottky diodes with reduced contact size and minimum series resistance between the n and n+ regions. Processing steps used are: patterning of SiO/sub 2/, n/sup +/ activation by rapid thermal annealing, e-beam Al deposition, and Al patterning. After fabricating the diodes, RF power detecting characteristics are measured by directly irradiating chips with RF power. In some cases, we also injected power by contact probes.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116167489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
A two-dimensional numerical simulation of a cylindrical resonant tunneling structure using a parallelized two-dimensional lattice Weyl-Wigner transport model 利用平行二维晶格Weyl-Wigner输运模型对圆柱共振隧道结构进行二维数值模拟
International Semiconductor Device Research Symposium, 2003 Pub Date : 2003-12-10 DOI: 10.1109/ISDRS.2003.1272069
G. Recine, B. Rosen, H. Cui
{"title":"A two-dimensional numerical simulation of a cylindrical resonant tunneling structure using a parallelized two-dimensional lattice Weyl-Wigner transport model","authors":"G. Recine, B. Rosen, H. Cui","doi":"10.1109/ISDRS.2003.1272069","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272069","url":null,"abstract":"We have recently developed a Buot-Jensen type lattice Weyl-Wigner 2D single band transport computer code which examines two-dimensional transport through a nanoscale quantum device exhibiting circular cylindrical symmetry. By performing the simulation in two dimensions, we are including radial effects in the Wigner function transport equation (WFE) which are not present in any one-dimensional simulation. We will describe the progress and process of constructing our simulation applied to a resonant tunneling structure (RTS) which can be described as a series of cylindrical shell RTSs, each having circular summary. We compare and contrast the results to an analogous structure simulated in one-dimension. The effect of radial drift, scattering and charge distribution will de discussed.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116501583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of PVD HfO/sub 2/MIM capacitors for Si RF and mixed signal ICs application 用于Si射频和混合信号集成电路的PVD HfO/sub /MIM电容器的研究
International Semiconductor Device Research Symposium, 2003 Pub Date : 2003-12-10 DOI: 10.1109/ISDRS.2003.1272118
Hang Hu, S. Ding, Chunxiang Zhu, S. Rustagi, Y. Lu, M. F. Li, B. Cho, D. Chan, M. Yu, A. Chin, D. Kwong
{"title":"Investigation of PVD HfO/sub 2/MIM capacitors for Si RF and mixed signal ICs application","authors":"Hang Hu, S. Ding, Chunxiang Zhu, S. Rustagi, Y. Lu, M. F. Li, B. Cho, D. Chan, M. Yu, A. Chin, D. Kwong","doi":"10.1109/ISDRS.2003.1272118","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272118","url":null,"abstract":"The electrical characteristics of high-/spl kappa/ PVD HfO/sub 2/ metal-insulator-metal (MIM) capacitors from IF (10 KHz) to RF (20 GHz) frequency range is investigated in this paper. High-/spl kappa/ HfO/sub 2/ dielectric with two thicknesses of 22 and 47 nm are fabricated, the respective capacitance densities are 7.3 and 3.5 fF//spl mu/m/sup 2/ and the two samples are denoted as HfO-1 to HfO-2. To investigate the capacitance characteristics of HfO/sub 2/ MIM capacitors in RF regime, the equivalent circuit model for capacitance is established. Thickness dependence of stress induced leakage currents (SILCs) for HfO/sub 2/ MIM capacitors is observed from J-V characteristics. For the C-V characteristics of HfO/sub 2/ MIM capacitors, the distortion of C-V curve after stress was reflected by the reduction of quadratic coefficients, exhibiting a flatten-out characteristic.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114986921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Blue electroluminescence from MOS capacitors with Si-implanted SiO/sub 2/ 硅注入SiO/sub / 2/ MOS电容器的蓝色电致发光
International Semiconductor Device Research Symposium, 2003 Pub Date : 2003-12-10 DOI: 10.1109/ISDRS.2003.1272012
T. Matsuda, M. Kawabe, K. Nishihara, H. Iwata, S. Iwatsubo, T. Ohzone
{"title":"Blue electroluminescence from MOS capacitors with Si-implanted SiO/sub 2/","authors":"T. Matsuda, M. Kawabe, K. Nishihara, H. Iwata, S. Iwatsubo, T. Ohzone","doi":"10.1109/ISDRS.2003.1272012","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272012","url":null,"abstract":"In this work, we demonstrate blue electroluminescence (EL) from Au/SiO/sub 2//p-Si MOS capacitor with Si implanted SiO/sub 2/. The transparent Au gate not only improves measurable wavelength range but also suppresses interference effects among MOS layers. The EL spectra have been successfully analysed by Gaussian distributions, and the EL mechanism is discussed. Gate current (J/sub G/) versus gate voltage (V/sub G/) characteristics under accumulation conditions was analysed. Blue EL spectra was observed and the measured data are successfully fitted by the Gaussian curves for EL mechanism analysis.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134133468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
LEDs for illumination: past, present and future led照明:过去，现在和未来
International Semiconductor Device Research Symposium, 2003 Pub Date : 2003-12-10 DOI: 10.1109/ISDRS.2003.1271953
C. Bohler
{"title":"LEDs for illumination: past, present and future","authors":"C. Bohler","doi":"10.1109/ISDRS.2003.1271953","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1271953","url":null,"abstract":"In this presentation, we discuss LEDs for general illumination lighting, focusing on properties of state of art, high brightness white LEDs. The is a paradigm shift associated with LED usage in the more traditional lighting applications. One aspect of this statement is demonstrated based on comparative energy distribution considerations of an LED lighting system. The low voltage, direct current (DC) electronic characteristics of an LED or LED array are illustrated.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133849187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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