Proceedings of International Workshop on Defect and Fault Tolerance in VLSI最新文献_第2页

Critical area extraction of extra material soft faults 附加物质软断层临界区提取

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476937

G. A. Allan, A. Walton

引用次数: 2

Using defect density modelling to drive the optimisation of circuit layout, maximising yield 使用缺陷密度模型来驱动电路布局的优化，最大限度地提高产量

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476949

M. Baxter, D. Muir

引用次数: 0

Characterization and analysis of errors in circuit test 电路测试误差的表征与分析

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476960

T. Ziaja, E. Swartzlander

引用次数: 1

Yield projection from defect monitors: the influence of gross defects [BiCMOS process] 缺陷监视器的良率预测:总体缺陷的影响[BiCMOS工艺]

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476947

Neil Harrison

引用次数: 2

Accurate yield estimation of circuits with redundancy 具有冗余电路的精确良率估计

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476948

D. Gaitonde, D. Walker, W. Maly

引用次数: 4

Self-checking FSMs based on a constant distance state encoding 基于定距状态编码的自校验FSMs

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476961

C. Bolchini, R. Montandon, F. Salice, D. Sciuto

引用次数: 12

A row-based FPGA for single and multiple stuck-at fault detection 用于单个和多个卡在故障检测的基于行FPGA

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476956

Xiao-Tao Chen, Wei-Kang Huang, F. Lombardi, Xiao Sun

{"title":"A row-based FPGA for single and multiple stuck-at fault detection","authors":"Xiao-Tao Chen, Wei-Kang Huang, F. Lombardi, Xiao Sun","doi":"10.1109/DFTVS.1995.476956","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476956","url":null,"abstract":"This paper presents a practical and low cost design-for-testability (DFT) scheme for the row-based field programmable gate array (FPGA) which is widely used for rapid prototyping, hardware verification/emulation of VLSI chips and manufacturing of complex digital systems. A new module is introduced for the DFT of the FPGA. The proposed DFT scheme permits the uncommitted FPGA to be tested using a set of constant cardinality (C-testability) for single and multiple stuck-at fault detection, while reducing the number of required primary test pins to only one. The number of tests for the FPGA is still 8+n/sub f/ (where n/sub f/ is the number of sequential modules in a row of the array), but only one primary pin and a small amount of testing circuitry are now required. This paper also modifies the single fault test set to accomplish multiple fault detection under two multiple fault models: the multiple fault single module (MFSM) and the single fault multiple module (SFMM) models. It is shown that by appropriately changing the don't care entries in the vectors of the test set for single fault detection, 100% and nearly 100% fault coverages can be achieved under the MFSM and SFMM models respectively.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"2021 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133159722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Bit-modular defect/fault-tolerant convolvers 位模缺陷/容错卷积

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476941

L. Dadda, V. Piuri

引用次数: 1

A study of time redundant fault tolerance techniques for superscalar processors 超标量处理器的时间冗余容错技术研究

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476954

M. Franklin

引用次数: 57

Totally defect-tolerant arrays capable of quick broadcasting 完全容错阵列，能够快速广播

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476944

N. Tsuda, T. Ishikawa, Yukihiro Nakamura

{"title":"Totally defect-tolerant arrays capable of quick broadcasting","authors":"N. Tsuda, T. Ishikawa, Yukihiro Nakamura","doi":"10.1109/DFTVS.1995.476944","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476944","url":null,"abstract":"This paper proposes an advanced spare-connection scheme for k-out-of-n redundancy called \"generalized additional bypass linking (ABL)\" for total defect-tolerance in large hybrid-WSIs with array structures. The proposed scheme uses bypass links with wired-OR connections to spare processing elements (PEs) without external switches, and can reconfigure complete arrays by tolerating defects in these PEs, links, and external I/O-terminals. The wired-OR connections help to limit the increase in the PE-connections of spare PEs, and these connections are made so that the primary PEs are an inter-PE distance of 3 or more away from each other and are connected to the same bypass link in parallel. The ABL scheme can be used for constructing totally defect-tolerant (TDT) arrays capable of quick broadcasting by using spare circuitries, and it is superior to conventional schemes in terms of extra PE-connections and control of the reconfiguration. This paper describes the basic ABL configurations for series-connected arrays, two-dimensional mesh-connected arrays, and binary trees, and further describes a hierarchical application of the ABL scheme that allows the construction of large arrays using shorter bypass links than the basic ABL configurations.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128304287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5