Proceedings of International Workshop on Defect and Fault Tolerance in VLSI最新文献_第4页

A channel-constrained reconfiguration approach for processing arrays 处理阵列的通道约束重构方法

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476942

M. Sami, F. Distante, R. Stefanelli

引用次数: 1

ADTS: an array defect-tolerance scheme for wafer scale gate arrays ADTS:用于晶圆级栅极阵列的阵列缺陷容限方案

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476945

A. Singh

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引用次数: 1

FFT-based test of a yield monitor circuit 基于fft的良率监测电路测试

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476958

C. Thibeault, A. Payeur

引用次数: 0

Cost analysis of a new algorithmic-based soft-error tolerant architecture 一种新的基于算法的软容错架构的成本分析

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476952

Y. Blaquière, G. Gagné, Y. Savaria, C. Évéquoz

引用次数: 0