A channel-constrained reconfiguration approach for processing arrays

Abstract

Most previous reconfiguration approaches considered as main figure of merit, besides probability of survival, length of reconfigured paths and deduced complexity of the interconnection network from the resulting algorithm. In the present paper, interconnection complexity is taken as the guiding figure of merit and a reconfiguration algorithm based on a stringent channel width limitation is presented. Performances are seen to be very good; furthermore, the solution can be extended to a comprehensive fault model, allowing presence of faults in bus segments and switches as well as in PEs.