Proceedings of International Workshop on Defect and Fault Tolerance in VLSI最新文献

Hierarchical extraction of critical area for shorts in very large ICs 超大集成电路中短路临界区域的分层提取

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476933

P. Nag, Wojciech Maly

引用次数: 51

Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosis 利用多芯片模块中的备件实现故障覆盖和故障诊断的双重功能

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476957

S. Goldberg, S. Upadhyaya

{"title":"Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosis","authors":"S. Goldberg, S. Upadhyaya","doi":"10.1109/DFTVS.1995.476957","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476957","url":null,"abstract":"Defining a dual role for spare processing elements (PEs) in reliability-challenged processing arrays is the major focus of the paper. The paper also explores a practical way to include reconfiguration hardware in single-package arrays. The implementation of array processor systems may include spare PE's for fault tolerance. These systems typically require a host for fault diagnosis, while the healthy spares sit idle. It is proposed to utilize the idling spare PEs for purposes of fault diagnosis, giving the array the capability of self diagnosis. Fault tolerance must incorporate additional hardware for reconfiguration, and existing plans have not found widespread use in single-package systems due to the extra cost and extra real estate. Multichip modules (MCMs) have the potential to offer fault tolerance with no increase in primary circuit area. It is proposed to contain the reconfiguration hardware in the active substrate of a silicon-based MCM. Further, the switches required for spares coverage can aid in the job of comparison based self-testing. We offer a complete solution to fault-tolerant arrays in the sense that diagnosis, reconfiguration and switching details are all addressed.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128513975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Hierarchical critical area extraction with the EYE tool 用EYE工具分层提取关键区域

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476934

G. A. Allan, A. Walton

引用次数: 29

The effect of spot defects on the parametric yield of long interconnection lines 点缺陷对长互连线参数良率的影响

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476936

I. Wagner, I. Koren

引用次数: 9

Repair algorithms for mirrored disk systems 镜像磁盘系统的修复算法

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476955

H. Kari, Heikki Saikkonen, Sungsoo Kim, F. Lombardi

引用次数: 2

Constructions of the SbEC-DbED and DbEC codes, and their applications sbc - dbed和DbEC规范的构建及其应用

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476962

G. Feng, Sihai Xiao, Xiaofa Shi, T. Rao

引用次数: 0

Efficient time redundancy for error correcting inner-product units and convolvers 有效的时间冗余纠错内积单元和卷积

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476953

Y. Hsu, V. Piuri, E. Swartzlander

引用次数: 13

Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths 分析和综合容错数据路径的高效算法

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476940

R. Narasimhan, D. Rosenkrantz, S. Ravi

{"title":"Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths","authors":"R. Narasimhan, D. Rosenkrantz, S. Ravi","doi":"10.1109/DFTVS.1995.476940","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476940","url":null,"abstract":"We address optimization problems arising in the synthesis of application specific integrated circuits (ASICs) that recover from transient faults via a rollback and retry approach. In this approach, each segment of a computation is duplicated and the results are compared using comparators. If the compared values are unequal, the computation is rolled back to the beginning of the segment (rollback point) and retried. Previous work in this area has generally been of an experimental nature focusing on heuristic approaches. We examine these problems from an algorithmic perspective. Several comparison and rollback strategies for reducing hardware costs and the delay caused by a transient fault have been previously proposed. For various combinations of these comparison and rollback strategies, we present efficient algorithms to analyze a given design to determine the maximum delay that can be caused by a transient fault of a given duration. These algorithms are based on formal characterizations of when a transient fault can cause a maximum delay for each combination of comparison and rollback strategies. We have also developed an efficient algorithm for designing fault-tolerant datapaths under hardware and delay constraints.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114806283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

An improved approach to fault tolerant rank order filtering on a SIMD mesh processor 一种改进的SIMD网格处理器容错秩序滤波方法

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476946

Jai-hoon Kim, F. Lombardi, N. Vaidya

引用次数: 2

Layer assignment for yield enhancement 提高产量的分层分配

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476950

Zhan Chen, I. Koren

引用次数: 12