{"title":"提高产量的分层分配","authors":"Zhan Chen, I. Koren","doi":"10.1109/DFTVS.1995.476950","DOIUrl":null,"url":null,"abstract":"In this paper, two algorithms for layer assignment with the goal of yield enhancement are proposed. In the first, vias in an existing layout are moved in order to decrease its sensitivity to defects. A greedy algorithm for achieving this objective is presented. In the second, we formulate the layer assignment problem as a network bipartitioning problem. By applying the primal-dual algorithm (a variation of the Kernighan-Lin algorithm), the objective of critical area minimization can be achieved. These two methods are applied to a set of benchmark circuits to demonstrate their effectiveness.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Layer assignment for yield enhancement\",\"authors\":\"Zhan Chen, I. Koren\",\"doi\":\"10.1109/DFTVS.1995.476950\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, two algorithms for layer assignment with the goal of yield enhancement are proposed. In the first, vias in an existing layout are moved in order to decrease its sensitivity to defects. A greedy algorithm for achieving this objective is presented. In the second, we formulate the layer assignment problem as a network bipartitioning problem. By applying the primal-dual algorithm (a variation of the Kernighan-Lin algorithm), the objective of critical area minimization can be achieved. These two methods are applied to a set of benchmark circuits to demonstrate their effectiveness.\",\"PeriodicalId\":362167,\"journal\":{\"name\":\"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-11-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1995.476950\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1995.476950","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, two algorithms for layer assignment with the goal of yield enhancement are proposed. In the first, vias in an existing layout are moved in order to decrease its sensitivity to defects. A greedy algorithm for achieving this objective is presented. In the second, we formulate the layer assignment problem as a network bipartitioning problem. By applying the primal-dual algorithm (a variation of the Kernighan-Lin algorithm), the objective of critical area minimization can be achieved. These two methods are applied to a set of benchmark circuits to demonstrate their effectiveness.