FFT-based test of a yield monitor circuit

Abstract

In this paper, we present a simple way to improve an existing electrical defect identification and location method. We show that replacing the DC voltage analysis by an FFT voltage analysis allows to reduce by a factor of about two the number of test vectors required to locate and identify defects on a yield monitor chip. Moreover, we suggest a minor modification to the monitor, doubling the reduction factor. Simulations results show that the location and identification potential is preserved.