{"title":"基于fft的良率监测电路测试","authors":"C. Thibeault, A. Payeur","doi":"10.1109/DFTVS.1995.476958","DOIUrl":null,"url":null,"abstract":"In this paper, we present a simple way to improve an existing electrical defect identification and location method. We show that replacing the DC voltage analysis by an FFT voltage analysis allows to reduce by a factor of about two the number of test vectors required to locate and identify defects on a yield monitor chip. Moreover, we suggest a minor modification to the monitor, doubling the reduction factor. Simulations results show that the location and identification potential is preserved.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"124 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"FFT-based test of a yield monitor circuit\",\"authors\":\"C. Thibeault, A. Payeur\",\"doi\":\"10.1109/DFTVS.1995.476958\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a simple way to improve an existing electrical defect identification and location method. We show that replacing the DC voltage analysis by an FFT voltage analysis allows to reduce by a factor of about two the number of test vectors required to locate and identify defects on a yield monitor chip. Moreover, we suggest a minor modification to the monitor, doubling the reduction factor. Simulations results show that the location and identification potential is preserved.\",\"PeriodicalId\":362167,\"journal\":{\"name\":\"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI\",\"volume\":\"124 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-11-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1995.476958\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1995.476958","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we present a simple way to improve an existing electrical defect identification and location method. We show that replacing the DC voltage analysis by an FFT voltage analysis allows to reduce by a factor of about two the number of test vectors required to locate and identify defects on a yield monitor chip. Moreover, we suggest a minor modification to the monitor, doubling the reduction factor. Simulations results show that the location and identification potential is preserved.