{"title":"处理阵列的通道约束重构方法","authors":"M. Sami, F. Distante, R. Stefanelli","doi":"10.1109/DFTVS.1995.476942","DOIUrl":null,"url":null,"abstract":"Most previous reconfiguration approaches considered as main figure of merit, besides probability of survival, length of reconfigured paths and deduced complexity of the interconnection network from the resulting algorithm. In the present paper, interconnection complexity is taken as the guiding figure of merit and a reconfiguration algorithm based on a stringent channel width limitation is presented. Performances are seen to be very good; furthermore, the solution can be extended to a comprehensive fault model, allowing presence of faults in bus segments and switches as well as in PEs.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"12386 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A channel-constrained reconfiguration approach for processing arrays\",\"authors\":\"M. Sami, F. Distante, R. Stefanelli\",\"doi\":\"10.1109/DFTVS.1995.476942\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Most previous reconfiguration approaches considered as main figure of merit, besides probability of survival, length of reconfigured paths and deduced complexity of the interconnection network from the resulting algorithm. In the present paper, interconnection complexity is taken as the guiding figure of merit and a reconfiguration algorithm based on a stringent channel width limitation is presented. Performances are seen to be very good; furthermore, the solution can be extended to a comprehensive fault model, allowing presence of faults in bus segments and switches as well as in PEs.\",\"PeriodicalId\":362167,\"journal\":{\"name\":\"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI\",\"volume\":\"12386 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-11-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1995.476942\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1995.476942","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A channel-constrained reconfiguration approach for processing arrays
Most previous reconfiguration approaches considered as main figure of merit, besides probability of survival, length of reconfigured paths and deduced complexity of the interconnection network from the resulting algorithm. In the present paper, interconnection complexity is taken as the guiding figure of merit and a reconfiguration algorithm based on a stringent channel width limitation is presented. Performances are seen to be very good; furthermore, the solution can be extended to a comprehensive fault model, allowing presence of faults in bus segments and switches as well as in PEs.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
