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Proceedings of International Workshop on Defect and Fault Tolerance in VLSI最新文献

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Wafer-scale integration defect avoidance tradeoffs between laser links and Omega network switching 晶圆级集成缺陷避免在激光链路和Omega网络交换之间的权衡
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476935
G. Chapman, D. E. Bergen, K. Fang
{"title":"Wafer-scale integration defect avoidance tradeoffs between laser links and Omega network switching","authors":"G. Chapman, D. E. Bergen, K. Fang","doi":"10.1109/DFTVS.1995.476935","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476935","url":null,"abstract":"Area, signal delay, and power consumption requirements are obtained in both 3 micron and 1.5 micron CMOS for two wafer scale defect avoidance methods: laser linking and active switching. In laser linking, focused laser power is used at each site to interconnect and cut bus lines. Active switching elements, such as the Omega network, enable real-time defect bypassing for self healing reconfigurations. Comparisons using simulations and fabricated device measurements of an Omega switch relative to laser links shows the area ranges from 5 to 11 times larger (respectively for the 1.5 and 3 micron processes), it requires an extra 18 to 25 nsec of signal delay and cell drivers to consume 60% more power than the laser links. Laser linked signal paths are so much faster than active switches that they effectively bypass failed switches without introducing significant extra delay. Thus a superior defect avoidance switch combines laser links and the Omega switch into a single unit.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133405219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout AFFCCA:用于圆缺陷和光刻变形布局的临界区域分析工具
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476932
Igor Bubel, W. Maly, T. Waas, P. Nag, H. Hartmann, D. Schmitt-Landsiedel, S. Griep
{"title":"AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout","authors":"Igor Bubel, W. Maly, T. Waas, P. Nag, H. Hartmann, D. Schmitt-Landsiedel, S. Griep","doi":"10.1109/DFTVS.1995.476932","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476932","url":null,"abstract":"This paper describes the AFFCCA (Accurate, Fast, Flexible Computation of Critical Area) tool. The algorithms implemented in AFFCCA can handle arbitrary geometry, defects causing shorts of arbitrary shapes, and a spectrum of process induced layout deformations. The presented results indicate that the unique features of AFFCCA allow for significant improvements in the accuracy of critical area computations.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122615649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Reconfigurable architectures for mesh-arrays with PE and link faults 具有PE和链路故障的网格阵列的可重构结构
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476943
I. Takanami, T. Horita
{"title":"Reconfigurable architectures for mesh-arrays with PE and link faults","authors":"I. Takanami, T. Horita","doi":"10.1109/DFTVS.1995.476943","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476943","url":null,"abstract":"We propose reconstruction architectures for mesh-arrays with link faults as well as processor element (PE) faults. First, we explain a method for compensating link faults and give a compensation algorithm for the case where no PE is faulty. Then, the reliabilities of the proposed interconnection networks are obtained by computer simulation and are compared with that of the network with doubly duplicated links. Next, we show how PE faults are compensated using the proposed network. It is seen that when no link is faulty, the ability of compensation is greater than that of the reconstruction strategy using single-track switches but is less than that of the strategy allowing the horizontal or vertical compensation paths to the spares on the boundary of mesh-arrays to cross. Finally considering that the proposed architectures have several routes to connect healthy PEs with each other, avoiding faulty PE, we propose an algorithm for coping with simultaneous faults of PEs and interconnection links.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114761577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analyzing and improving delay defect tolerance in pipelined combinational circuits 流水线组合电路中延迟缺陷容忍度的分析与改进
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476951
D. Wessels, J. Muzio
{"title":"Analyzing and improving delay defect tolerance in pipelined combinational circuits","authors":"D. Wessels, J. Muzio","doi":"10.1109/DFTVS.1995.476951","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476951","url":null,"abstract":"In this paper, we consider the problems of identification of delay-fault-sensitive components in a pipelined combinational circuit, and of circuit modification to improve the circuit's tolerance of delay faults. The results assume purely combinational logic, and fixed gate delays calculated under floating delay mode.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133362388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Single fault masking logic designs with error correcting codes 带有纠错码的单故障屏蔽逻辑设计
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476964
Jien-Chung Lo
{"title":"Single fault masking logic designs with error correcting codes","authors":"Jien-Chung Lo","doi":"10.1109/DFTVS.1995.476964","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476964","url":null,"abstract":"Triple modular redundancy (TMR) has been the most popular method in reliable logic designs due to a single fault masking capability. However, the reliability of a TMR design can be improved only by enhancing the reliabilities of the components. This paper examines the use of error correcting codes in reliable logic design. The goal is to provide an equivalent single fault masking capability as that of TMR scheme. Further, by reducing the level of hardware redundancy, a higher reliability can be achieved. Design examples are given to illustrate the key issues in single fault masking logic designs with error correcting codes. Reliabilities of different single fault masking carry lookahead adder designs are also examined.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131088315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Novel Berger code checker 新颖的伯杰代码检查器
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476963
C. Metra, M. Favalli, B. Riccò
{"title":"Novel Berger code checker","authors":"C. Metra, M. Favalli, B. Riccò","doi":"10.1109/DFTVS.1995.476963","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476963","url":null,"abstract":"This paper presents a novel checking circuit for Berger codes, with any value of k (also k=2/sup r-1/), which is TSC with respect to a wide set of realistic faults including all possible stuck-ats, transistors stuck-on/stuck-open, as well as several likely to occur resistive bridgings. With respect to the other alternative implementations the proposed checker features the advantage of being inherently more testable, and of requiring lower area overhead.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128912935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Approximation of critical area of ICs with simple parameters extracted from the layout 用从版图中提取的简单参数逼近集成电路的临界面积
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476931
F. Duvivier, M. Rivier
{"title":"Approximation of critical area of ICs with simple parameters extracted from the layout","authors":"F. Duvivier, M. Rivier","doi":"10.1109/DFTVS.1995.476931","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476931","url":null,"abstract":"In order to have an efficient yield model to compare and predict yields of different products for a fixed manufacturing process, it is necessary to measure a lot of parameters such as critical area of each mask level, yields of elementary process steps, etc. Obtaining values of all the required parameters in an industrial context is often very difficult, and the resulting yield model becomes almost useless, and at least very cumbersome to exploit. Simpler models have been proposed that often tradeoff simplicity for precision of the results. Most of these assume that the chip critical area is proportional to the die area. Other have used the number of transistors as a yardstick to compare chip yields for ASICs generated with a common design system. This paper proposes a new set of parameters derived from the layout of each chip that may be used to assess the yield of a new IC based on a known manufacturing process. This proposal is based on the results of several efficient statistical techniques that are described and applied to a database of approximately one million chips.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123980607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design of defect-tolerant scan chains for MCMs with an active substrate 带有有源衬底的mcm容错扫描链设计
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476959
P. Brahic, R. Leveugle, G. Saucier
{"title":"Design of defect-tolerant scan chains for MCMs with an active substrate","authors":"P. Brahic, R. Leveugle, G. Saucier","doi":"10.1109/DFTVS.1995.476959","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476959","url":null,"abstract":"The work presented in this paper aims at defining the best solution for designing defect-tolerant scan chains, taking into account the sensitivity of the yield improvement on various parameters. The results presented demonstrate that a noticeable yield increase can be achieved, but only if the selected redundant architecture is coherent with the implementation details, in particular the multiplexer electrical structure. It is also shown that the most straightforward approach, i.e., the triple modular redundancy, can be very inefficient if optimized majority gates are not available for the implementation.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124337014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A model for the evaluation of fault tolerance in the FERMI system FERMI系统容错性评估模型
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476939
A. Antola, L. Breveglieri
{"title":"A model for the evaluation of fault tolerance in the FERMI system","authors":"A. Antola, L. Breveglieri","doi":"10.1109/DFTVS.1995.476939","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476939","url":null,"abstract":"Experiments of high energy physics planned at the Large Hadron Collider (LHC) at CERN (CH) require digital data acquisition systems with high throughput. Such systems need also be fault tolerant to the permanent and transient faults induced by radiation, since they must be installed close to the experiment area. A model for the evaluation of the fault tolerance performances of the most significant VLSI devices designed for the construction of the FERMI system, a data acquisition system for the LHC, is presented. The model allows one to quantify the probability of the FERMI system to survive fatal failures, to increase mission time and to provide valid data for different implementations of fault tolerance.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"56 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120870947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Switch level hot-carrier reliability enhancement of VLSI circuits VLSI电路开关级热载流子可靠性增强
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI: 10.1109/DFTVS.1995.476938
A. Dasgupta, R. Karri
{"title":"Switch level hot-carrier reliability enhancement of VLSI circuits","authors":"A. Dasgupta, R. Karri","doi":"10.1109/DFTVS.1995.476938","DOIUrl":"https://doi.org/10.1109/DFTVS.1995.476938","url":null,"abstract":"Long-term reliability of MOS VLSI circuits is becoming an important issue with rapid advances in VLSI technology and increasing VLSI chip densities. Hot-carrier effects and electromigration are the two important failure mechanisms that significantly impact the long-term reliability of high-density VLSI ICs. In this paper, we present a probabilistic switch-level method for identifying MOSFETs in the circuit that are most susceptible to hot-carrier effects. Subsequently, we outline two techniques-(i) reordering of inputs to logic gates and (ii) selective MOSFET siting-to reduce the hot-carrier susceptibility of these critical MOSFETs. Finally, we show that for a given circuit, the best design in terms of hot-carrier reliability does not necessarily coincide with the best design in terms of power consumption. The algorithms are incorporated into SIS and are evaluated on the ISCAS-MCNC91 benchmark suite.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126793622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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