流水线组合电路中延迟缺陷容忍度的分析与改进

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI Pub Date : 1995-11-13 DOI:10.1109/DFTVS.1995.476951

D. Wessels, J. Muzio

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引用次数: 3

摘要

本文研究了流水线组合电路中延迟故障敏感元件的识别问题，以及改进电路以提高电路对延迟故障的容忍度的问题。结果假设纯组合逻辑，并在浮动延迟模式下计算固定门延迟。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analyzing and improving delay defect tolerance in pipelined combinational circuits

In this paper, we consider the problems of identification of delay-fault-sensitive components in a pipelined combinational circuit, and of circuit modification to improve the circuit's tolerance of delay faults. The results assume purely combinational logic, and fixed gate delays calculated under floating delay mode.

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Proceedings of International Workshop on Defect and Fault Tolerance in VLSI

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