{"title":"Design of defect-tolerant scan chains for MCMs with an active substrate","authors":"P. Brahic, R. Leveugle, G. Saucier","doi":"10.1109/DFTVS.1995.476959","DOIUrl":null,"url":null,"abstract":"The work presented in this paper aims at defining the best solution for designing defect-tolerant scan chains, taking into account the sensitivity of the yield improvement on various parameters. The results presented demonstrate that a noticeable yield increase can be achieved, but only if the selected redundant architecture is coherent with the implementation details, in particular the multiplexer electrical structure. It is also shown that the most straightforward approach, i.e., the triple modular redundancy, can be very inefficient if optimized majority gates are not available for the implementation.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1995.476959","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The work presented in this paper aims at defining the best solution for designing defect-tolerant scan chains, taking into account the sensitivity of the yield improvement on various parameters. The results presented demonstrate that a noticeable yield increase can be achieved, but only if the selected redundant architecture is coherent with the implementation details, in particular the multiplexer electrical structure. It is also shown that the most straightforward approach, i.e., the triple modular redundancy, can be very inefficient if optimized majority gates are not available for the implementation.