ADTS: an array defect-tolerance scheme for wafer scale gate arrays

Abstract

Current attempts at wafer scale integration all involve restructuring the circuits on the wafer following fabrication to purge out the effects of manufacturing defects. This requires expensive restructuring techniques, and only works for regular designs such as memories and processor arrays. Here we propose a novel low cost approach for defect tolerance in gate array based systems, which does not require restructuring, and is not limited to array structures. Our proposed approach takes advantage of the fact that gate array implementations typically do not use all the available gates in the array. The idea is to first test all the base wafers and obtain a defect map for each wafer, listing the faulty gates. Then only those wafers are used to implement a given design whose defective gates map to unused gates in the design. We show that with a novel use of redundancy in the physical gate array, we can ensure a high probability of finding a compatible wafer for a given design. Furthermore, wafers that are unsuitable for one design can be used for a different design with a different pattern of unused gates. The analysis presented here suggests, for example, that for gate arrays containing 20 defects, (which can be expected to be an order of magnitude larger in area than current die sizes) a pool of a hundred different designs is sufficient to ensure that virtually all the wafers manufactured will be utilized. Thus our proposed new approach holds out the promise of low cost WSI gate array systems for low volume special purpose applications, with no restrictions on the system architecture. This does not appear possible from any of the other WSI strategies being currently pursued.