{"title":"位模缺陷/容错卷积","authors":"L. Dadda, V. Piuri","doi":"10.1109/DFTVS.1995.476941","DOIUrl":null,"url":null,"abstract":"Design of a family of high-throughput modular convolvers is discussed, with particular reference to the defect and fault tolerance issues. The proposed architecture is based on parallel computation for the individual operands' bits with final merging of the partial results. Different degrees of defect/fault tolerance are considered for different production and operational environments. Modularity is exploited to support also functional adaptability.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Bit-modular defect/fault-tolerant convolvers\",\"authors\":\"L. Dadda, V. Piuri\",\"doi\":\"10.1109/DFTVS.1995.476941\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Design of a family of high-throughput modular convolvers is discussed, with particular reference to the defect and fault tolerance issues. The proposed architecture is based on parallel computation for the individual operands' bits with final merging of the partial results. Different degrees of defect/fault tolerance are considered for different production and operational environments. Modularity is exploited to support also functional adaptability.\",\"PeriodicalId\":362167,\"journal\":{\"name\":\"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-11-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1995.476941\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1995.476941","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a family of high-throughput modular convolvers is discussed, with particular reference to the defect and fault tolerance issues. The proposed architecture is based on parallel computation for the individual operands' bits with final merging of the partial results. Different degrees of defect/fault tolerance are considered for different production and operational environments. Modularity is exploited to support also functional adaptability.