Accurate yield estimation of circuits with redundancy

Yield concerns owing to increasing die sizes have prompted designers to include redundant elements in the design. In this paper we present a technique for accurately estimating the yield of designs that employ redundancy. We show that conventional techniques that do not take into account the actual chip layout and defect statistics could result in substantial error in the yield estimate. We show that the optimum amount and nature of redundancy depends heavily on the nature of the the circuit, the chip layout and defect statistics.