{"title":"完全容错阵列,能够快速广播","authors":"N. Tsuda, T. Ishikawa, Yukihiro Nakamura","doi":"10.1109/DFTVS.1995.476944","DOIUrl":null,"url":null,"abstract":"This paper proposes an advanced spare-connection scheme for k-out-of-n redundancy called \"generalized additional bypass linking (ABL)\" for total defect-tolerance in large hybrid-WSIs with array structures. The proposed scheme uses bypass links with wired-OR connections to spare processing elements (PEs) without external switches, and can reconfigure complete arrays by tolerating defects in these PEs, links, and external I/O-terminals. The wired-OR connections help to limit the increase in the PE-connections of spare PEs, and these connections are made so that the primary PEs are an inter-PE distance of 3 or more away from each other and are connected to the same bypass link in parallel. The ABL scheme can be used for constructing totally defect-tolerant (TDT) arrays capable of quick broadcasting by using spare circuitries, and it is superior to conventional schemes in terms of extra PE-connections and control of the reconfiguration. This paper describes the basic ABL configurations for series-connected arrays, two-dimensional mesh-connected arrays, and binary trees, and further describes a hierarchical application of the ABL scheme that allows the construction of large arrays using shorter bypass links than the basic ABL configurations.","PeriodicalId":362167,"journal":{"name":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Totally defect-tolerant arrays capable of quick broadcasting\",\"authors\":\"N. Tsuda, T. Ishikawa, Yukihiro Nakamura\",\"doi\":\"10.1109/DFTVS.1995.476944\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes an advanced spare-connection scheme for k-out-of-n redundancy called \\\"generalized additional bypass linking (ABL)\\\" for total defect-tolerance in large hybrid-WSIs with array structures. The proposed scheme uses bypass links with wired-OR connections to spare processing elements (PEs) without external switches, and can reconfigure complete arrays by tolerating defects in these PEs, links, and external I/O-terminals. The wired-OR connections help to limit the increase in the PE-connections of spare PEs, and these connections are made so that the primary PEs are an inter-PE distance of 3 or more away from each other and are connected to the same bypass link in parallel. The ABL scheme can be used for constructing totally defect-tolerant (TDT) arrays capable of quick broadcasting by using spare circuitries, and it is superior to conventional schemes in terms of extra PE-connections and control of the reconfiguration. This paper describes the basic ABL configurations for series-connected arrays, two-dimensional mesh-connected arrays, and binary trees, and further describes a hierarchical application of the ABL scheme that allows the construction of large arrays using shorter bypass links than the basic ABL configurations.\",\"PeriodicalId\":362167,\"journal\":{\"name\":\"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-11-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFTVS.1995.476944\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Workshop on Defect and Fault Tolerance in VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1995.476944","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Totally defect-tolerant arrays capable of quick broadcasting
This paper proposes an advanced spare-connection scheme for k-out-of-n redundancy called "generalized additional bypass linking (ABL)" for total defect-tolerance in large hybrid-WSIs with array structures. The proposed scheme uses bypass links with wired-OR connections to spare processing elements (PEs) without external switches, and can reconfigure complete arrays by tolerating defects in these PEs, links, and external I/O-terminals. The wired-OR connections help to limit the increase in the PE-connections of spare PEs, and these connections are made so that the primary PEs are an inter-PE distance of 3 or more away from each other and are connected to the same bypass link in parallel. The ABL scheme can be used for constructing totally defect-tolerant (TDT) arrays capable of quick broadcasting by using spare circuitries, and it is superior to conventional schemes in terms of extra PE-connections and control of the reconfiguration. This paper describes the basic ABL configurations for series-connected arrays, two-dimensional mesh-connected arrays, and binary trees, and further describes a hierarchical application of the ABL scheme that allows the construction of large arrays using shorter bypass links than the basic ABL configurations.