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Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.最新文献

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10-transistor 1-bit adders for n-bit parallel adders 用于n位并行加法器的10晶体管1位加法器
Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI: 10.1109/ICM.2004.1434237
F. Vasefi, Z. Abid
{"title":"10-transistor 1-bit adders for n-bit parallel adders","authors":"F. Vasefi, Z. Abid","doi":"10.1109/ICM.2004.1434237","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434237","url":null,"abstract":"Two designs of 10-transistor 1-bit adder are described in this paper. The output voltages levels of these 1-bit adders have a maximum of one threshold voltage (V/sub T/) loss. This is an important property since previously described 10-transistor designs suffer from two-threshold voltage loss. This also allows the successful use of these designs in a 4-bit ripple carry adder (RCA) and a 12-bit carry select adder (CSA). This is the first time where both the 4-bit and the 12-bit adders operate properly while using a 10-transistors 1-bit adder. All these circuits are implemented and simulated in 0.18 /spl mu/m CMOS technology using Cadence development tools. The average power dissipation and maximum time delay have been recorded.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115586169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CMOS integrated micromachined inductive microphone CMOS集成微机械感应传声器
Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI: 10.1109/ICM.2004.1434219
Fares Tounsi, M. Jallouli, B. Mezghani, S. Smaoui, N. Ghamgui, M. Masmoudi
{"title":"CMOS integrated micromachined inductive microphone","authors":"Fares Tounsi, M. Jallouli, B. Mezghani, S. Smaoui, N. Ghamgui, M. Masmoudi","doi":"10.1109/ICM.2004.1434219","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434219","url":null,"abstract":"A novel silicon micromachined inductive microphone has been proposed, designed and analyzed. The microphone is fabricated on a single wafer by the use of bulk micromachining technology that is post-processing on substrates containing integrated circuits (IC's), independently of the IC process. The working principle of this pressure sensor is based on inductance coupling between an external fixed inductor and an internal suspended inductor. Due to mutual inductance effect on vibrating the internal inductor, we obtain a varying voltage proportional to the amplitude variation of the incident wave. This internal inductor is designed on a 4-lever double turn suspended membrane. When compared with the single turn structure, it is found to be much more flexible. For the double turn structure, we intend to make a study of the variation of the mutual inductance and its derivative under the effect of two main factors. The first factor to study be the number of turns in the secondary and the primary inductors, which we choose to be the same. The suspended membrane dimensions constitute the second factor to study. We notice that the first factor has a bigger effect on the mutual inductance and on the output voltage.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114363648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Room temperature electroluminescence from metal oxide-silicon surface-barrier diode 金属氧化物-硅表面势垒二极管的室温电致发光
Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI: 10.1109/ICM.2004.1434701
O. Malik, V. Grimalsky, A. Torres-J, J. De la Hidalga-W
{"title":"Room temperature electroluminescence from metal oxide-silicon surface-barrier diode","authors":"O. Malik, V. Grimalsky, A. Torres-J, J. De la Hidalga-W","doi":"10.1109/ICM.2004.1434701","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434701","url":null,"abstract":"Room temperature electroluminescence (EL) corresponding to silicon band gap energy is observed from ITO-nSi surface-barrier diodes fabricated by a spray pyrolysis technique, where ITO is a transparent conducting film of tin-doped indium oxide. This film is separated from silicon by a thin interfacial SiO/sub x/ layer about of 10 /spl Aring/ thick grown on the silicon surface in hydrogen peroxide solution. The work functions of ITO and Si are such that surface n-type silicon layer is inverted to p type, and induced a p/sup +/-n junction is formed at the surface of the silicon. The tunneling current through SiO/sub x/ layer provides an ohmic contact between ITO and surface-induced p-Si layer. Distinction of investigated structures is a significant minority-carrier injection ratio about 0.35 determined from examination of ITO-nSi-ITO transistor behavior. The injection ratio can reach the value of 0.8 when the potential barrier height on Si surface is 0.9 eV. High-efficiency EL was investigated under excitation with forward biased short (10-200 /spl mu/s) current pulses up to 500 A/cm/sup 2/. Spectral dependence of EL is connected with radiative recombination of injected electron-hole plasma.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114657102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Optimized VLSI design of wavelet transform architecture 优化VLSI的小波变换架构设计
Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI: 10.1109/ICM.2004.1434724
C. Souani
{"title":"Optimized VLSI design of wavelet transform architecture","authors":"C. Souani","doi":"10.1109/ICM.2004.1434724","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434724","url":null,"abstract":"This paper presents a VLSI implementation of one dimensional direct discrete wavelet transform. We propose a new architecture using parallel filters. We consider the implementation of 1-D three levels DWT. The proposed architecture is simple and offers 16-bit precision on input and output data. No memory or registers are used for storing intermediate results. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches. The architecture can compute DWT at a data rate of 7/spl times/10/sup 6/ samples/s corresponding to a typical clock speed of 7 MHz with 3.2 V of operate voltage. Process parameters used were those of 0.35 /spl mu/m technology. The chip area is about 2 mm/sup 2/.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117073746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Structural, chemical and magnetic characterization of electrodeposited CoFeCu material 电沉积CoFeCu材料的结构、化学和磁性表征
Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI: 10.1109/ICM.2004.1434752
B. Benfedda, N. Benbrahim, A. Adri, Y. Dahmane
{"title":"Structural, chemical and magnetic characterization of electrodeposited CoFeCu material","authors":"B. Benfedda, N. Benbrahim, A. Adri, Y. Dahmane","doi":"10.1109/ICM.2004.1434752","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434752","url":null,"abstract":"Electrodeposition of the iron group metals (Fe, Co, Ni) magnetic thin films has attracted much attention due to their potential applications in computer read/write heads. Electrodeposition is an inexpensive method for generating films with a high technological potential. Most investigation studied the effects of processing deposition condition such as pH, temperature, surtension, additives. In this present work, we propose to study the effect of boric acid and potential on the electrodeposition of CoFeCu. Film thickness was measured with the quartz crystal of the electrochemical quartz microbalance (EQCM) and composition was determined by energy dispersive X-ray spectroscopy (EDX). Crystalline structure was investigated by X-ray diffraction (XRD). The magnetic properties were determined by vibrating sample magnetometer (VSM). It was found that increasing the boric acid concentration affects the structure and the composition of the formed CoFeCu. The morphology of deposits as a function of the boric acid concentration was investigated by SEM. It reveals a smooth surface with regular grain size for the different boric acid concentration. CoFeCu prepared exhibits a Bs value of 19 to 20 KG and a coercive field more than 50e.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123493859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling and optimization of mixed logic circuits: the CMOS/CPL combination 混合逻辑电路的建模与优化:CMOS/CPL组合
Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI: 10.1109/ICM.2004.1434603
Y. Wan, M. Shams
{"title":"Modeling and optimization of mixed logic circuits: the CMOS/CPL combination","authors":"Y. Wan, M. Shams","doi":"10.1109/ICM.2004.1434603","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434603","url":null,"abstract":"Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. In this paper, the combination of standard CMOS with CPL is examined with an eye to finding the best structure and the best insertion points for CMOS buffers intended to improve a CPL chain's propagation time and drive capability.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116856995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the degradation of organic field-effect transistors 论有机场效应晶体管的退化
Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI: 10.1109/ICM.2004.1434210
C. Pannemann, T. Diekmann, U. Hilleringmann
{"title":"On the degradation of organic field-effect transistors","authors":"C. Pannemann, T. Diekmann, U. Hilleringmann","doi":"10.1109/ICM.2004.1434210","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434210","url":null,"abstract":"Degradation experiments with organic thin film transistors (OTFT) made of the p-conducting organic semiconductor pentacene revealed a distinct dependence of the electrical transistor parameters to the ambient conditions. A sample that was kept unprotected in dark ambient air conditions was found to be still operating after 9 months of degradation. The on-current was reduced by one order of magnitude per quarter year and the threshold voltage shifted to negative values. To study the influence of the respective gases of the atmosphere, an OTFT was characterized in vacuum conditions and exposed to the distinct gases. The exposure of the unprotected organic film to oxygen resulted in a decreasing on-current, on-off ratio and a positive shift of the threshold voltage, due to scattering centers formed by the reaction of oxygen with the pentacene. Nitrogen caused a decrease of the on-current with reversible tendency when the vacuum conditions were re-established.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129721673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Frequency analysis of integrated micromachined inductive microphone 集成微机械感应式传声器的频率分析
Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI: 10.1109/ICM.2004.1434245
M. Jallouli, Fares Tounsi, B. Mezghani, S. Smaoui, M. Masmoudi
{"title":"Frequency analysis of integrated micromachined inductive microphone","authors":"M. Jallouli, Fares Tounsi, B. Mezghani, S. Smaoui, M. Masmoudi","doi":"10.1109/ICM.2004.1434245","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434245","url":null,"abstract":"This paper is focused on frequency analysis of integrated micromachined inductive microphone. It is a very important step in the conception of integrated sensors. The concept of this new structure is based on the variation of mutual inductance between an external fixed inductor and an internal suspended inductor. The internal inductor is fabricated on top of a suspended membrane. Our goal is to increase the resonant frequencies of the suspended structure. We propose a new model of a membrane to the monolithic CMOS integrated inductive microphone. We studied the dynamic response. The choice of the new model is derived and discussed. The frequencies and the associated mode shapes determined by finite element analysis using SOLIDWORKS and COSMOSWORKS with technology AMS 0.8 /spl mu/m, are described. The purpose is to demonstrate a sensibility of the microphone.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128162178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low voltage, highly linear CMOS OTA 低电压，高线性CMOS OTA
Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI: 10.1109/ICM.2004.1434762
A. El mourabit, P. Pittet, G. Lu
{"title":"A low voltage, highly linear CMOS OTA","authors":"A. El mourabit, P. Pittet, G. Lu","doi":"10.1109/ICM.2004.1434762","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434762","url":null,"abstract":"This paper presents, a new configuration of linear CMOS subthreshold operational transconductance amplifier (LSOTA) working at 1.5 V with very low power consumption. Based on FGMOS technique, the developed OTA has a wide input range and small Gm, suitable for implementing low frequency analog and monolithic continuous-time filters. For demonstration a low pass second order filter was designed and simulated. The power consumption of the filter is less than 2 /spl mu/W and the topology achieves 76 dB linearity for fully balanced input dynamic range up to 1 Vpp at 1.5 V supply voltage.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129795754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Characterization and modelling of power RF LDMOS transistor including self-heating effects 功率RF LDMOS晶体管的特性与建模，包括自热效应
Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI: 10.1109/ICM.2004.1434262
M. Belaid, H. Maanane, K. Mourgues, M. Masmoudi, K. Ketata, J. Marcon
{"title":"Characterization and modelling of power RF LDMOS transistor including self-heating effects","authors":"M. Belaid, H. Maanane, K. Mourgues, M. Masmoudi, K. Ketata, J. Marcon","doi":"10.1109/ICM.2004.1434262","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434262","url":null,"abstract":"In this paper, we propose a new electro-thermal model of power RF LDMOS transistor implemented in Agilent's ADS, using symbolic defined device (SDD). The proposed model takes into account the thermal effects and influence of temperature on the I-V characteristics, by providing three thermal capacitances and three thermal resistances, which represent the heat flow from the chip to the ambient air (thermal network). It allows us to study temperature dependent shifts for some macroscopic parameters such as the threshold voltage (V/sub t/), the transconductance (g/sub m/), the conductance (g/sub d/) and the on-state resistance (R/sub ds-on/).","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127209247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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