Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.最新文献

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A prototyping platform based on a PCI micronetwork and Leon multiprocessor system 基于PCI微网络和Leon多处理器系统的原型平台
F. Berthelot, D. Houzet, F. Nouvel
{"title":"A prototyping platform based on a PCI micronetwork and Leon multiprocessor system","authors":"F. Berthelot, D. Houzet, F. Nouvel","doi":"10.1109/ICM.2004.1434776","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434776","url":null,"abstract":"System-on-chip (SoC) designs provide integrated solutions to challenging design problems in the telecommunication, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers ability to conceive complex electronic engines under strong time to market pressure. Success relies on using appropriate design and process technologies, on the ability to interconnect existing components including processors, controllers, and memory array reliably as well as on the capability to validate such complex designs. This last point is the topic of this paper, which presents a prototyping methodology and flexible hardware platform developed to facilitate rapid prototyping and validation of such telecommunication systems.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127368893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimizing low-power high-speed full adders with simulated annealing 模拟退火法优化低功耗高速全加法器
A. Amirabadi, Y. Mortazavi, A. Afzali-Kusha
{"title":"Optimizing low-power high-speed full adders with simulated annealing","authors":"A. Amirabadi, Y. Mortazavi, A. Afzali-Kusha","doi":"10.1109/ICM.2004.1434605","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434605","url":null,"abstract":"In this paper, a random search algorithm known as simulated annealing (SA) has been employed to optimize the sizing of a number of digital adder circuits. The SA algorithm is implemented in MATLAB; the cost function, a function of power and delay, is accurately computed using HSPICE for a 0.35 /spl mu/m technology. Using a piecewise linear and logarithmic cost function, the delay and power is optimized in an intelligent fashion. The results show a 60% reduction in power and a 65% reduction in delay with respect to previous designs based on analytical calculations.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128927291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a FPGA based data acquisition system for radio astronomy applications 基于FPGA的射电天文数据采集系统设计
Y. Abhyankar, C. Sajish, P. Kulkarni, C. R. Subrahmanya
{"title":"Design of a FPGA based data acquisition system for radio astronomy applications","authors":"Y. Abhyankar, C. Sajish, P. Kulkarni, C. R. Subrahmanya","doi":"10.1109/ICM.2004.1434723","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434723","url":null,"abstract":"In this paper, we describe a high-speed, PCI based data acquisition system using a Xilinx FPGA for very long baseline interferometry. This system accepts data through LVDS interface and has time keeping options through external clocks for providing an accurate time tagging on the acquired data. It has provision for on-line flagging on selective data samples. Using the host interface, the system can communicate for data transfer through DMA. User can allocate multiple buffers in the host memory where the acquired data can be transferred. The system is very useful for a variety of high-speed signal processing applications in radio astronomy and other areas.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130759698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Mapping of high-bit algorithm to low-bit for optimized hardware implementation 高位算法到低位算法的映射,以优化硬件实现
S. Farhan, Shoab A. Khan, Habibullah Jamal
{"title":"Mapping of high-bit algorithm to low-bit for optimized hardware implementation","authors":"S. Farhan, Shoab A. Khan, Habibullah Jamal","doi":"10.1109/ICM.2004.1434230","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434230","url":null,"abstract":"This paper presents the outcome of a novel technique for mapping a class of high data width algorithms to low data width for efficient hardware implementation. The complexity of mapping an algorithm in hardware directly depends upon the data path size as all the registers and computational blocks depend on this size. Reducing the data path requirement can result in substantial savings in hardware. Folding techniques classically reduce the bit-widths. Our techique reduces the data path width without folding or timesharing the hardware resources. The technique is implemented on the advanced encryption standard (AES) algorithm and substantial savings in hardware cost is reported. Using this technique the 32-bit AES is implemented on a byte-systolic 8-bit architecture. The proposed crypto processor architecture resulted in efficient hardware resource utilization reducing data-path, buses, registers and memories to 8-bits, minimizing control logic, area and power. Unlike commercially available AES architectures, which incorporate separate hardware modules for key expansion, the proposed crypto processor design reuses the same architecture for both key expansion and encryption. The proposed design offers moderately high data rates when mapped on FPGA.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123203074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Efficient and cost effective approach to control and monitoring area network (CMAN) 高效、经济的控制和监测局域网(CMAN)方法
A. Hashmi, H.W. Malik, A. Pervaiz, M. Younas
{"title":"Efficient and cost effective approach to control and monitoring area network (CMAN)","authors":"A. Hashmi, H.W. Malik, A. Pervaiz, M. Younas","doi":"10.1109/ICM.2004.1434761","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434761","url":null,"abstract":"This paper provides an efficient and cost effective solution for controlling and monitoring domestic and industrial electrical devices. Our solution works on a standard local area network using a specially designed hardware interfaced with an embedded Ethernet system using PIC microcontroller. During the course of the project, we developed various solutions to detect the status of any electrical appliance, to transmit its status over the LAN, and to control it using any PC having Internet access. We have modified the ICMP packets for communication among various components of our system. We have modified the data field of the ICMP ping packet into subfields of header and status indicators.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123079271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An optimized CMOS second generation current conveyor 一种优化的CMOS第二代电流输送装置
S. Bensalem, M. Fakhfakh, A. Sallem, M. Loulon, N. Masmoudi
{"title":"An optimized CMOS second generation current conveyor","authors":"S. Bensalem, M. Fakhfakh, A. Sallem, M. Loulon, N. Masmoudi","doi":"10.1109/ICM.2004.1434738","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434738","url":null,"abstract":"A high performance second generation current conveyor (CCII) is presented in this paper. It has a current bandwidth of 1.8 GHz and a 4.52 GHz voltage transfer characteristic. Also, it gives 0.0016% and 0.0064% for voltage and current THD respectively, 0.003% and 0.015 as current and voltage relative errors respectively and -2.67 mV and -0.684 /spl mu/A as voltage and current offsets. The heuristic used to reach such performances is also detailed. SPICE simulation results are presented to show the good reached results.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122296180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A hardware/software co-design approach for face recognition 人脸识别的硬件/软件协同设计方法
Xiaoguang Li, S. Areibi
{"title":"A hardware/software co-design approach for face recognition","authors":"Xiaoguang Li, S. Areibi","doi":"10.1109/ICM.2004.1434204","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434204","url":null,"abstract":"Face recognition is a technique employed in large-scale citizen identification applications, surveillance applications, law enforcement applications such as booking stations, and kiosks. Artificial neural networks (ANNs) have been proved to be an effective way to solve this problem, but due to the long-time training process, this approach cannot be implemented efficiently by software. Although, hardware implementations can speedup the training process, this may lead to an inflexible solution. To balance flexibility (i.e., software implementations) and performance (i.e., hardware implementations), an embedded computing system consisting of both a processor and dedicated hardware on a field programmable gate array (FPGA) chip is proposed to solve face recognition based on an ANN approach. Results obtained indicate that this system achieves almost twice the speedup over a pure software implementation.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115301125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
A new leakage-tolerant design for high fan-in domino circuits 高扇入多米诺电路的新型耐漏设计
F. Moradi, A. Peiravi, H. Mahmoodi
{"title":"A new leakage-tolerant design for high fan-in domino circuits","authors":"F. Moradi, A. Peiravi, H. Mahmoodi","doi":"10.1109/ICM.2004.1434707","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434707","url":null,"abstract":"In this paper, a new leakage-tolerant circuit design technique for high fan-in domino circuits is presented. This technique uses stacking effect to reduce the leakage of the evaluation network of domino gates. It also uses a current mirror in parallel with the evaluation network to reduce the evaluation delay. Depending on the fan-in, the proposed technique exhibits 2.0X to 17.7X leakage and noise tolerance improvement compared to a standard domino counterparts designed in a 70-nm technology node.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116602090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Component selection for SoC SoC的元件选择
A. Adnen, A. Mtibaa
{"title":"Component selection for SoC","authors":"A. Adnen, A. Mtibaa","doi":"10.1109/ICM.2004.1434775","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434775","url":null,"abstract":"The current densities of the integration on chip allow the implantation on a same circuit of the applications dedicated for multimedia services, according to three possible approaches: a software approach which consists of programming cores of microprocessors or DSPs, an approach dedicated that leads to realize a specific core to the application and an approach using a dynamic reconfiguration of the components offered by \"design reuse\". This paper presents a study of the dynamic reconfiguration and/or static in the systems on chip aiming at the integration of the accelerators into the multimedia applications in order to exploit the contribution offered by the dynamic reconfiguration and to orientate toward the concept of the SoC programmable (SoPC). On the other hand, the time allowed for the choice of the virtual components constitutes a challenging conception imposed by the increase of IPs providers. Indeed, our objective consists of developing a tool permitting the automation of the selection and the reuse of the VCs (virtual component) and to optimize the choice of the adequate solution based on criteria linked to the restraints of the environment (area availability, time of execution and power).","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123837055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Parallel FPGA implementation of self-organizing maps 自组织映射的并行FPGA实现
K. Ben Khalifa, B. Girau, F. Alexandre, M. H. Bedoui
{"title":"Parallel FPGA implementation of self-organizing maps","authors":"K. Ben Khalifa, B. Girau, F. Alexandre, M. H. Bedoui","doi":"10.1109/ICM.2004.1434765","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434765","url":null,"abstract":"This paper presents an area-saving parallel implementation of a self-organizing map neural network (SOM) on FPGA. The purpose is to make available a finer grain of parallelism to be used in massively SIMD parallel SOM system architectures. We have handled a serial arithmetics (most significant bit first: MSBF and least significant bit first: LSBF), to process the different mathematical operations. Above all, our work has been oriented in such a way to get a light, easy to wear system for classification of vigilance states in humans from electroencephalographic (EEG) signals. The performances of our implementation in terms of area, speed and especially power consumption are highly satisfactory.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114001039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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