高扇入多米诺电路的新型耐漏设计

Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI:10.1109/ICM.2004.1434707

F. Moradi, A. Peiravi, H. Mahmoodi

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引用次数: 30

摘要

本文提出了一种新的高扇入多米诺电路容漏电路设计技术。该技术利用叠加效应减少了多米诺门评价网络的泄漏。它还使用了一个与评估网络并行的电流镜像，以减少评估延迟。根据扇入的不同，与采用70纳米技术节点设计的标准多米诺骨牌相比，该技术的泄漏和噪声容限提高了2.0到17.7倍。

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A new leakage-tolerant design for high fan-in domino circuits

In this paper, a new leakage-tolerant circuit design technique for high fan-in domino circuits is presented. This technique uses stacking effect to reduce the leakage of the evaluation network of domino gates. It also uses a current mirror in parallel with the evaluation network to reduce the evaluation delay. Depending on the fan-in, the proposed technique exhibits 2.0X to 17.7X leakage and noise tolerance improvement compared to a standard domino counterparts designed in a 70-nm technology node.

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Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.

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