M. Avram, G. Brezeanu, D. Poenar, M. Simion, C. Voitincu
{"title":"Contributions to development of IGBT on SiC technologies","authors":"M. Avram, G. Brezeanu, D. Poenar, M. Simion, C. Voitincu","doi":"10.1109/ICM.2004.1434589","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434589","url":null,"abstract":"A punch through insulated gate bipolar transistor realized on silicon carbide (4H-SiC) is presented. The IGBT chip consists of a parallel connection of ten thousands elementary cells. The cell equivalent circuit is designed with a MOSFET and a bipolar transistor in a Darlington configuration. The IGBT presented in this paper has one epilayer (cheaper), a buffer layer between substrate and epilayer to improve the dynamic characteristics and a guard ring/epilayer junction to increase the saturation current.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116082328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Andrei, O. Valorge, F. Calmon, J. Verdier, C. Gontrand
{"title":"Impact of substrate perturbation on a 5 GHz VCO spectrum","authors":"C. Andrei, O. Valorge, F. Calmon, J. Verdier, C. Gontrand","doi":"10.1109/ICM.2004.1434758","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434758","url":null,"abstract":"This work investigates substrate coupling effects in mixed IC's, especially the perturbations on RF block. The authors present the impact of low frequency substrate noise perturbations on voltage-controlled oscillator (VCO) spectrum. A 5 GHz VCO test-chip is presented; several substrate taps have been placed inside VCO core to measure or to inject noise perturbations. The oscillation frequency sensitivity function of tuning voltage or bias current and spurious side-bands due to injected noise are measured to find out a relation between substrate noise and spectrum purity. Finally, a significant link between such device sensitivity functions and VCO spurs magnitude is demonstrated.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114729154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Abdallah, S. Pillement, O. Sentieys, A. Bouallègue
{"title":"Acceleration of a VLIW processor with dynamic reconfiguration","authors":"F. Abdallah, S. Pillement, O. Sentieys, A. Bouallègue","doi":"10.1109/ICM.2004.1434745","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434745","url":null,"abstract":"Apart from prototyping, reconfigurable architectures find mainly their utility in speeding up the arithmetic or logical treatments. To achieve this goal, it is possible to use a reconfigurable architecture to discharge the processor host from the too complex treatments or for which it is not adapted. The complexity of the treatments entrusted to the coprocessor then varies according to the mode of coupling between this last and the host processor which even influences the cost of communications. This research examines the role of dynamically reconfigurable logic in systems-on-chip (SOC) design. Specifically, in this paper, we carried out the modes of coupling the dynamically configurable cluster DART with a VLIW processor. The implementation of a WCDMA receiver allowed to make qualitative study of various techniques of coupling and to evaluate the performances of the Lx/DART architecture.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117023333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Ghariani, M. W. Kharrat, N. Masmoudi, L. Kamoun
{"title":"Electronic implementation of a neural observer in FPGA technology application to the control of electric vehicle","authors":"M. Ghariani, M. W. Kharrat, N. Masmoudi, L. Kamoun","doi":"10.1109/ICM.2004.1434611","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434611","url":null,"abstract":"This paper presents a new integration approach for the control of an induction machine in the FPGA technology. The proposal is based on the design of an adaptive observer that makes it possible to generate the induction machine parameters in real time. The proposed observer is based on the use of neural networks whose their generalisation capacity allows the compensation of the induction machine parameter variations. Considering the enormous algorithmic resources requested by the neural network integration, an optimised architecture of the observer is proposed using CORDIC algorithm. It makes it possible to show the best performances in time and area on the technology SPARTAN of XILINX.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115117241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An auto-sensitivity control circuit for wired CDMA bus interface","authors":"Mostafa A. R. Eltokhy","doi":"10.1109/ICM.2004.1434770","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434770","url":null,"abstract":"We had proposed an auto-sensitivity control circuit for DS-CDMA receiver circuit. The wired bus interface requires different sensitivities for different number of transmitter/receiver pairs. These changes make errors in the receiving data. We proposed circuit that controls the effect of using different numbers of transmitter/receiver pairs. Simulation results verified that with the auto-sensitivity control circuit, receiver circuit in DS-CDMA wired bus interface works well for range of 8 to 40 pairs of transmitter/receiver.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123194119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hadi Esmaelzadeh, Hamed Farshbaf, Carlos P. Lucas, D. M. Fakhraie
{"title":"Digital implementation for conic section function networks","authors":"Hadi Esmaelzadeh, Hamed Farshbaf, Carlos P. Lucas, D. M. Fakhraie","doi":"10.1109/ICM.2004.1434725","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434725","url":null,"abstract":"A digital implementation is presented for a neural network, which uses conic section function neurons. This network is employed in a digit pattern recognition application. The neural network is trained without any consideration about non-idealities of hardware implementation and then obtained weight parameters are converted to fixed-point bit-string format in order to match hardware implementation. Controlling the number of bits used in this conversion, forces a trade off between accurate operation of the network and size of the hardware. Finding the optimum number of bits, steps are taken for implementation of network. Simulation results in different levels of the prepared design flow are presented.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123554291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An analytical approach to hardware-friendly adaptive learning rate neural networks","authors":"M. Ghannad Rezaie, F. Farbiz, S. M. Fakhraie","doi":"10.1109/ICM.2004.1434278","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434278","url":null,"abstract":"In this paper hardware implementation of adaptive learning rate neural networks is studied. Some design guidelines are presented to improve integration of learning algorithm into the hardware. By using them, it is possible to design high performance neural networks, which are capable of handling a rapidly-conversing learning algorithm in analog chips. The analytical approach developed in this work provides more insight towards tuning of a reliable design. Our experimental results prove that this approach performs above the conventional fixed learning rate approach, and is almost comparable to the ideal gradient based adaptive approach.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115619414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Model for electrical simulation of photogate active pixel sensor","authors":"B. Casadei, Y. Hu, C. Dufaza, L. Martín","doi":"10.1109/ICM.2004.1434242","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434242","url":null,"abstract":"A new electrical simulation model for photogate active pixel sensor in CMOS imagers is proposed. Review of three conventional models is done and shows lack of accuracy. Therefore photoelectric mechanisms and charges transfer of photogate pixel are analysed and lead to the definition of a Verilog-A description model. This model is then simulated into the Cadence design tool environment and simulation results show great improvements in simulation accuracy of the proposed model versus others ones.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"477 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123391672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Rail-to-rail differential linear range OTA with pico-A/V transconductance for subHertz OTA-C filter","authors":"A. El mourabit, G. Lu, P. Pittet","doi":"10.1109/ICM.2004.1434749","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434749","url":null,"abstract":"This paper presents a new configuration of a rail-to-rail subthreshold OTA with very small transconductance suitable for implementing extreme low frequency filter. We exploit the intrinsic property of dc-level translation of multiple input floating gate (MIFG) transistor by serially stacking such devices in diode connected configuration as source degeneration of a subthreshold OTA which achieves simultaneously rail-to-rail differential linear range and very small transconductance. Under 2 V supply voltage, the total harmonic distortion (THD) is less than 1% for 2 Vpp input. The transconductance range is 15-150 pS for a biasing current of 1-100 nA while the total power consumption is kept below 2 /spl mu/W.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128704427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and realization of wireless technologies for alarm systems","authors":"F. Derbel","doi":"10.1109/ICM.2004.1434273","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434273","url":null,"abstract":"This paper presents important factors for designing wireless systems as well as two types of wireless communications for alarm systems with short-range radio for the industrial (SIGMASPACE) and the residential (SiRoute) markets. Those systems have been designed to fulfill the different market requirements, especially regarding reaction times in case of alarms and disturbances and batteries lifetime. The SIGMASPACE is designed as a hybrid system including many gateways on the wired communication bus and master slave communication fulfilling the EN54 standards. The SiRoute system is based on a multi-hop mesh network that allows low battery power consumption, high ranges in buildings independently of structures and reaction times according to EN 50131-1. The wireless communication is performed in an exclusive frequency band for short-range devices by 868 MHz with regulated effective radiated powers and transmission duration (duty cycle).","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126522677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}