Acceleration of a VLIW processor with dynamic reconfiguration

Abstract

Apart from prototyping, reconfigurable architectures find mainly their utility in speeding up the arithmetic or logical treatments. To achieve this goal, it is possible to use a reconfigurable architecture to discharge the processor host from the too complex treatments or for which it is not adapted. The complexity of the treatments entrusted to the coprocessor then varies according to the mode of coupling between this last and the host processor which even influences the cost of communications. This research examines the role of dynamically reconfigurable logic in systems-on-chip (SOC) design. Specifically, in this paper, we carried out the modes of coupling the dynamically configurable cluster DART with a VLIW processor. The implementation of a WCDMA receiver allowed to make qualitative study of various techniques of coupling and to evaluate the performances of the Lx/DART architecture.