混合逻辑电路的建模与优化:CMOS/CPL组合

Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI:10.1109/ICM.2004.1434603

Y. Wan, M. Shams

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引用次数: 0

摘要

在单一技术逻辑电路中实现最大速度的有效优化方法广泛可用，但适用于涉及逻辑族混合的电路的系统方法还没有。本文研究了标准CMOS与CPL的结合，旨在寻找CMOS缓冲器的最佳结构和最佳插入点，以提高CPL链的传播时间和驱动能力。

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Modeling and optimization of mixed logic circuits: the CMOS/CPL combination

Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. In this paper, the combination of standard CMOS with CPL is examined with an eye to finding the best structure and the best insertion points for CMOS buffers intended to improve a CPL chain's propagation time and drive capability.

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Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.

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