Optimized VLSI design of wavelet transform architecture

Abstract

This paper presents a VLSI implementation of one dimensional direct discrete wavelet transform. We propose a new architecture using parallel filters. We consider the implementation of 1-D three levels DWT. The proposed architecture is simple and offers 16-bit precision on input and output data. No memory or registers are used for storing intermediate results. The end result is an efficient VLSI implementation with a reduced area cost compared to the conventional approaches. The architecture can compute DWT at a data rate of 7/spl times/10/sup 6/ samples/s corresponding to a typical clock speed of 7 MHz with 3.2 V of operate voltage. Process parameters used were those of 0.35 /spl mu/m technology. The chip area is about 2 mm/sup 2/.