2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)最新文献_第3页

Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells 节能finfet与基于tfet的STT-MRAM位单元

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789086

Ariana Musello, Santiago S. Pérez, M. Villegas, L. Prócel, R. Taco, L. Trojman

引用次数: 1

Improved Approximate Multipliers for Single-Precision Floating-Point Hardware Design 单精度浮点硬件设计的改进近似乘法器

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789077

Patrícia U. L. da Costa, P. Pereira, B. Abreu, Guilherme Paim, E. Costa, S. Bampi

引用次数: 4

Low Power Frequency Dividers using TSPC logic in 28nm FDSOI Technology 采用TSPC逻辑的28nm FDSOI技术的低功率分频器

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789073

Md. Sazzad Hossain, M. B. Moreira, Francois Sandrez, F. Rivet, H. Lapuyade, Y. Deval

引用次数: 1

Voltage-to-Voltage Sigmoid Neuron Activation Function Design for Artificial Neural Networks 人工神经网络的电压-电压s型神经元激活函数设计

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789075

Tatiana Moposita, L. Trojman, F. Crupi, M. Lanuzza, A. Vladimirescu

引用次数: 3

Memristor-based Oscillator for Complex Chemical Wave Logic Computations: Fredkin Gate Paradigm 用于复杂化学波逻辑计算的基于忆阻器的振荡器:弗雷德金门范式

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789083

Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, V. Ntinas, Stavros Kitsios, P. Bousoulas, Michail-Antisthenis I. Tsompanas, D. Tsoukalas, A. Adamatzky, G. Sirakoulis

{"title":"Memristor-based Oscillator for Complex Chemical Wave Logic Computations: Fredkin Gate Paradigm","authors":"Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, V. Ntinas, Stavros Kitsios, P. Bousoulas, Michail-Antisthenis I. Tsompanas, D. Tsoukalas, A. Adamatzky, G. Sirakoulis","doi":"10.1109/LASCAS53948.2022.9789083","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789083","url":null,"abstract":"Concurrent computational machines have not provided in all cases ideal or even efficient implementations for a range of complex and computationally expensive problems. Thus, the utilization of unconventional computing systems, often inspired by biological processes, is widely investigated. One characteristic category of these systems is chemical computers that encode reactants' spatial concentrations as information and employ wave-fronts' propagation as means of computation. The most widely known and used reaction is the Belousov-Zhabotinsky ($BZ$) that perfectly demonstrates non-equilibrium thermodynamics. Motivated by these chemical computers and to further enhance their analysis, a digital-twin was developed and tested. Namely MemRC, a memristor based oscillator is presented here. The ability of the proposed electrical circuitry to mimic the computational abilities of a chemical system was demonstrated by the realization of Fredkin gate operations. The results of the electrical system are in good agreement with results from simulation of the chemical medium and from laboratory experiments. Furthermore an important advantage of the electrical system is the significant acceleration of the computations that can enable further testing of possible implementations.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126719966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An integrated circuit to enable electrodeposition and amperometric readout of sensing electrodes 一种集成电路，可实现电沉积和感应电极的安培读数

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789069

Minghao Li, A. Vanhoestenberghe, S. Ghoreishizadeh

引用次数: 2

Random Number Generators Based on Metastable Behavior in Double-Scroll Chaotic Attractors 基于双涡旋混沌吸引子亚稳行为的随机数发生器

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789089

Kaya Demir, Salih Ergün

{"title":"Random Number Generators Based on Metastable Behavior in Double-Scroll Chaotic Attractors","authors":"Kaya Demir, Salih Ergün","doi":"10.1109/LASCAS53948.2022.9789089","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789089","url":null,"abstract":"This paper presents the numerical analysis, circuit implementation and simulation of a random number generator (RNG) exploiting the metastable behavior arising in a double scroll chaotic attractor. Random bits are generated by sampling a regular clock signal at times when a jump between scrolls of the chaotic attractor occurs. The double-scroll chaotic oscillator used in this study is implemented using mosfet transistors and metal-insulator-metal (mim) capacitors at 65nm TSMC process. The overall monolithic RNG circuit consists of a chaotic attractor, a Schmitt trigger and a dual edge triggered D flip-flop. The RNG circuit is simulated in time domain using Cadence Analog Design Environment. Then to generate the output bit stream, a regular clock signal is sampled when the chaotic signal jumps from one of the scrolls to the other representing the metastable characteristic of chaos. The event of jump between scrolls is detected using the mosfet based Schmitt trigger and an irregular clock signal is generated which is used to sample a regular clock signal by using a dual-edge triggered D flip-flop to generate RNG output. The generated bit stream is demonstrated to satisfy the NIST 800–22 statistical randomness test suite. The layout of the proposed RNG is also given along with the circuit schematic. The area of the RNG is approximately $0.004 mm^{2}$, the power consumption is $30 mu W$, and the data throughput is approximately $0.72 Mbps$.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125399079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 52.3% Peak Efficiency 22nm CMOS Low-Power Light-Adaptive Self-Oscillating Voltage Doubler Using Scalable Dynamic Leakage-Suppression Logic 一种峰值效率52.3%的22nm CMOS低功耗光自适应倍频器，采用可扩展的动态泄漏抑制逻辑

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789056

Xujiaming Chen, Guowei Chen, Xinyang Yu, Yue Wang, K. Niitsu

引用次数: 0

Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices 商用FPGA器件中的容错有限状态机准延迟不敏感

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789092

Orlando Verducci, D. L. Oliveira, G. Batista

{"title":"Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices","authors":"Orlando Verducci, D. L. Oliveira, G. Batista","doi":"10.1109/LASCAS53948.2022.9789092","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789092","url":null,"abstract":"Because electronic devices cannot avoid soft errors (unexpected and non-destructive signal transitions) occurred in radiation environment, circuit redundancy approaches are adopted for such situations, which lead to huge penalties in area and power dissipation resources in digital design. QDI-AFSM (Quasi-Delay Insensitive-Asynchronous Finite State Machine), which uses dual-rail variables, may be an interesting solution for fault-tolerant digital systems if some additional circuitry is used for soft errors detection. In FPGA, this issue is particularly concerning because, in such target devices, any digital circuitry is modeled using programmable LUTs (Look Up Tables) where a flipped bit cannot be recovered unless a new programming procedure be done. The proposed architecture for finite state machines in FPGA devices enhances robustness to a QDI digital design inserting a novel output register based on sequential logic gates that validate each dual-rail output variable on the system according to the current processing cycle and output state. The reduced average penalties in area, power, and latency for the proposed fault-tolerant architecture may be advantageous compared to TMR approaches.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132409951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures 片上无线通信在多核架构上的全面系统探索

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9893905

Rafael A. Medina, Joshua Kein, Y. Qureshi, Marina Zapater, G. Ansaloni, David Atienza Alonso

{"title":"Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures","authors":"Rafael A. Medina, Joshua Kein, Y. Qureshi, Marina Zapater, G. Ansaloni, David Atienza Alonso","doi":"10.1109/LASCAS53948.2022.9893905","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9893905","url":null,"abstract":"In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the “memory wall” are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recent advances in the integration of nano-antennas, enabling novel short-distance communication paradigms, promise disruptive gains. To gauge their potential benefit for the next-generation of many-core server designs, it is crucial to explore the impact of wireless communication links from a whole-system viewpoint, considering complex architectures and applications characteristics. To this end, in this work we introduce an extension to the popular gem5 full system-level simulator, enabling the simulation of many-core platforms featuring on-chip wireless channels. This new extension allows the flexible investigation of different combinations of wireless and wired interconnects, as well as diverse connection protocols. We showcase its capabilities by performing an architectural exploration, targeting a multi-core system executing image inference using an AlexNet Neural Network benchmark. A 2.3x speedup is obtained when implementing wireless communication between cores instead of traditional on-chip wired interconnects.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116101073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0