2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)最新文献

MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows MLSBench:基于FPGA HLS设计流程的机器学习基准集

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789084

Pingakshya Goswami, Masoud Shahshahani, D. Bhatia

{"title":"MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows","authors":"Pingakshya Goswami, Masoud Shahshahani, D. Bhatia","doi":"10.1109/LASCAS53948.2022.9789084","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789084","url":null,"abstract":"High-Level Synthesis (HLS) is becoming a defacto standard for starting large FPGA-based design projects. FPGA design flows are completely embracing HLS based methodologies so that software engineers with almost no hardware design skills can easily use their tools. Behavioral descriptions used during the high-level synthesis (HLS) are completely technology-independent, making it hard for designers to interpret how changes in the synthesis options affect the resultant circuit. Researchers across industry and academia are performing research in the field of machine-learning-based predictive high-level synthesis (HLS) tool design, where the quality of results (QOR) can be predicted using various ML techniques. One of the greatest challenges in all these works is the availability of open-source HLS designs on which the designers can train and predict their models. Generation of benchmarks is a time-consuming process and lack of availability of standard benchmarks prevents fair comparison among various proposed models. In this paper, we propose a methodology for generating diverse designs with various variations from a single design. We have created a data-set of more than 6000 synthesizable FPGA HLS designs written in C/C++ and System C. We provide a detailed statistical analysis of the generated benchmarks. The data set is available for public use. We have demonstrated the use of our data-set in case studies that involve quick model-based design space exploration.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121016448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

UAVs vs Satellites: Comparison of tools for water quality monitoring 无人机与卫星:水质监测工具的比较

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789059

Enzo Pacilio, Alejo Silvarrey, Á. Pardo

引用次数: 1

A Digital Random Number Generator Based on Four Regional Examination of Double Scroll Chaos 基于双涡旋混沌四区域检测的数字随机数发生器

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789090

Onur Karatas, Salih Ergün

{"title":"A Digital Random Number Generator Based on Four Regional Examination of Double Scroll Chaos","authors":"Onur Karatas, Salih Ergün","doi":"10.1109/LASCAS53948.2022.9789090","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789090","url":null,"abstract":"This paper presents the design of a novel random number generator (RNG) based on a new method. Digital Double scroll chaos is used as an RNG production source. Design is performed based on the regional examination of regular samples from a double scroll chaos system. The digital double scroll chaos used in this study is implemented by exploiting the nonlinearity of the sawtooth wave in a 3rd order ordinary differential equation (ODE). By analyzing the distributions of the chaotic state variables $x, y, z$ in 3-dimensions, it has been observed that they have an underlying distribution. The double scroll chaos is divided into four regions by preserving the characteristics of the underlying distributions, and binary data is obtained using each one of these four regions. These binary data are combined through a xor operation to generate the RNG output and a robust RNG is obtained. The proposed RNG is implemented using the Verilog hardware description language and is prototyped on the KCU105 Evaluation Board Xilinx FPGA. The proposed RNG is demonstrated to provide data throughput up to 13.25 Mbps. The RNG output satisfies all statistical randomness tests in the NIST 800-22 and TestU01 packages without post-processing.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120843888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design 动态低功耗超级栅极设计中逻辑功耗晶体管尺寸的校准

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789079

Henrique Kessler, Murilo Bohlke, L. Rosa, M. Porto, V. Camargo

引用次数: 0

Atrial Fibrillation Detection Using Weight-Pruned, Log-Quantised Convolutional Neural Networks 利用加权修剪、对数量化卷积神经网络检测心房颤动

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9893904

Xiu Qi Chang, Ann Feng Chew, Benjamin Chen Ming Choong, Shuhui Wang, Rui Han, W. He, Li Xiaolin, R. Panicker, Deepu John

引用次数: 0

SOI UTBB Capacitive Cross-Coupling Effects in Ultimate Technological Nodes 极限技术节点的电容交叉耦合效应

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789068

F. Costa, R. Trevisoli, R. Doria

引用次数: 0

An IoT SoC for Agricultural Applications 农业应用物联网SoC

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789071

V. Grimblatt, G. Ferré, F. Rivet, C. Jégo

{"title":"An IoT SoC for Agricultural Applications","authors":"V. Grimblatt, G. Ferré, F. Rivet, C. Jégo","doi":"10.1109/LASCAS53948.2022.9789071","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789071","url":null,"abstract":"The constant growth of the population and the diminution of the arable land is a threat for the Humankind. Technology applied to agriculture can save the Humankind from a food and climate crisis. Food and Agriculture Organization of the United Nations (FAO) recommends to increase agricultural production by 70 % in 2050. On the other hand, agriculture is one of the major contributors to the global warming while it is one of the most adversely affected by this global warming. Therefore, it is important to increase productivity while preserving planetary boundaries. In this challenging context we propose to monitor the growth and health of plants by handling on the field parameters such as soil moisture, soil pH, soil temperature, soil salinity, etc. In order to do this, an Internet of Things (IoT) system has been designed. This system is based on a versatile System on a Chip (SoC), using the LoRa protocol for transmission and a low-power energy scheme to operate independently. The SoC processes locally the parameters on the edge and sends data to the cloud for analysis and prediction. It takes automatic actions and provides recommendations to the farmer. Low power, versatility, adaptability, edge computing, ease of use and low cost are the main constraints of the IoT system and the designed SoC. This paper details the design of the SoC architecture including the used design flow and the main results based on the specifications.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"17 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120851235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Ultra-Low Power 22 nm Self-Oscillating Voltage Doubler With Dynamic Leakage-Suppression Logic 超低功耗22nm自振荡电压倍频器与动态漏阻逻辑

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789081

Sora Kato, Guowei Chen, K. Niitsu

引用次数: 0

Design of Asynchronous Pipelines with QDI Template Using Commercial FPGA 基于商用FPGA的QDI模板异步管道设计

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789066

Gabriel C. Duarte, D. L. Oliveira, G. Batista

引用次数: 0

Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region 基于近似的大性能区域最小能量点跟踪算法实现

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789067

Shoya Sonoda, Jun Shiomi, H. Onodera

{"title":"Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region","authors":"Shoya Sonoda, Jun Shiomi, H. Onodera","doi":"10.1109/LASCAS53948.2022.9789067","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789067","url":null,"abstract":"This paper refers to an optimal pair of the supply and the threshold voltages, which minimizes the energy consumption under the given delay constraint, as a minimum energy point (MEP). This paper proposes an approximation-based implementation method for an MEP tracking algorithm over a wide operating performance region. The key point is that the accuracy required for determining the MEP is not high. Even if the MEP estimated by the algorithm differs by a few tens of millivolts in comparison with the actual MEP, the energy loss introduced by the estimation error is small. Therefore, the complexity for determining the MEP can be reduced by approximating complex operations such as the logarithmic or the exponential functions in the MEP estimation algorithm, which leads to hardware-Isoftware-efficient implementation. Measurement results based on a 32-bit RISC-V processor fabricated in a 65-nm process technology show that the energy loss introduced by the proposed approximation is less than 1% in comparison with the MEP operation. When the MEP tracking algorithm is implemented in software, the MEP estimation time is reduced from 1 ms to 13 $mu mathrm{s}$. When implemented in hardware, the proposed method can reduce the area of an MEP estimation circuit to a quarter.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115254417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0