Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design

Abstract

Gate sizing has been widely studied to improve power dissipation and performance characteristics in VLSI design. Recent developments allow the automatic design of static CMOS complex gates for a reduction in power dissipation. It is possible to observe a lack of different transistor sizing in these works using minimum transistor dimension or the Logical Effort technique. In this work, we propose a methodology to adapt the Logical Effort technique for low-power applications. Results show significant improvements on up to 99.9% of the studied cases in power-performance trade-off across multiple simulation environments for a 45nm CMOS technology.