MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows

High-Level Synthesis (HLS) is becoming a defacto standard for starting large FPGA-based design projects. FPGA design flows are completely embracing HLS based methodologies so that software engineers with almost no hardware design skills can easily use their tools. Behavioral descriptions used during the high-level synthesis (HLS) are completely technology-independent, making it hard for designers to interpret how changes in the synthesis options affect the resultant circuit. Researchers across industry and academia are performing research in the field of machine-learning-based predictive high-level synthesis (HLS) tool design, where the quality of results (QOR) can be predicted using various ML techniques. One of the greatest challenges in all these works is the availability of open-source HLS designs on which the designers can train and predict their models. Generation of benchmarks is a time-consuming process and lack of availability of standard benchmarks prevents fair comparison among various proposed models. In this paper, we propose a methodology for generating diverse designs with various variations from a single design. We have created a data-set of more than 6000 synthesizable FPGA HLS designs written in C/C++ and System C. We provide a detailed statistical analysis of the generated benchmarks. The data set is available for public use. We have demonstrated the use of our data-set in case studies that involve quick model-based design space exploration.