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2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)最新文献

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A Wide-Range, High-Voltage, Floating Level Shifter with Charge Refreshing in a Standard 180 nm CMOS Process 标准180nm CMOS工艺中具有电荷刷新功能的宽量程、高压、浮动电平移位器
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789044
David Palomeque-Mangut, Á. Rodríguez-Vázquez, M. Delgado-Restituto
{"title":"A Wide-Range, High-Voltage, Floating Level Shifter with Charge Refreshing in a Standard 180 nm CMOS Process","authors":"David Palomeque-Mangut, Á. Rodríguez-Vázquez, M. Delgado-Restituto","doi":"10.1109/LASCAS53948.2022.9789044","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789044","url":null,"abstract":"A high-voltage (HV) floating level shifter which slides digital signals by varying the low supply rail from ground to V<inf>S</inf><inf>S</inf><inf>H</inf> while preserving the input signal swing is proposed. The cell is based on a periodically-refreshed charge pump circuit and it is suitable for non-HV CMOS processes. Input signals can be non-periodic. The circuit has been designed and implemented in a standard 180 nm 1.8V/3.3V CMOS node, occupying 0.02 mm<sup>2</sup>. Post-layout simulations show that V<inf>S</inf><inf>S</inf><inf>H</inf> voltage can safely range from 0.5 V to 9.5 V. The delay response of the circuit is 1.9 ns and it consumes 13.9 μW.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122270657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
26 GHz VCO in 22 nm FDSOI Technology for RADAR Application 雷达应用的22nm FDSOI技术的26ghz压控振荡器
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789048
Piyush Kumar, Dario Stajic, E. Isa, L. Maurer
{"title":"26 GHz VCO in 22 nm FDSOI Technology for RADAR Application","authors":"Piyush Kumar, Dario Stajic, E. Isa, L. Maurer","doi":"10.1109/LASCAS53948.2022.9789048","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789048","url":null,"abstract":"A novel modified-Colpitts-Differential Voltage Controlled Oscillator (VCO) is presented in this paper. The VCO is intended to be used in the application related to Frequency-Modulated-Continuous-Wave (FMCW) Radar. The VCO is de-signed to cover the frequency range from 23 GHz to 27.8 GHz. The RF output can be interfaced with a band-pass filter and an amplifier to obtain a clean third-harmonic spectrum. The VCO has drain-to-source feedback path and is realized using 22 nm FDSOI-CMOS technology from Globalfoundries. The paper covers design aspects, layout and simulation results of the fabricated VCO. The effect of process variation is also covered in this paper. The best simulated phase noise (@ 1 MHz offset) is -110.6 dBc/Hz at a central frequency of 24.5 GHz. The approximate overall power consumption of the VCO and buffer is 23 mW, and the circuit starts operating at a minimum-supply voltage of 700 mV. To stablize the frequency, VCO can be interfaced with other blocks of Phase-locked loop (PLL).","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126926636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ultra-Low-Power CMOS Voltage Reference Topologies Regarding Technology Node 关于技术节点的超低功耗CMOS电压参考拓扑
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789042
F. Olivera, L. S. D. Silva, A. Petraglia
{"title":"Ultra-Low-Power CMOS Voltage Reference Topologies Regarding Technology Node","authors":"F. Olivera, L. S. D. Silva, A. Petraglia","doi":"10.1109/LASCAS53948.2022.9789042","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789042","url":null,"abstract":"Ultra-low-power (ULP) designs have received great attention due to the emergence of a wide variety of devices of internet-of-things (IoT) applications. The scaling down of CMOS technology introduces additional challenges for designers, since circuit topologies are usually modified in order to maintain performance under the effects of the next technology. In this paper, a comparative study of ULP voltage references (VRs) is advanced considering four CMOS technologies: 180 nm (bulk), 90 nm (bulk), 65 nm (bulk) and 28 nm (FD-SOI). In addition, major nanometer effects such as drain induced barrier lowering (DIBL), gate induced drain leakage (GIDL), gate leakage due to direct tunneling, junction leakage, among others, are carefully considered in order to suggest an appropriated VR topology regarding each technology node.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130412894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Long-Range Low-Power Soil Water Content Monitoring System for Precision Agriculture 精准农业远程低功率土壤含水量监测系统
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789070
Mattia Barezzi, U. Garlando, Francesca Pettiti, L. Nari, D. Gisolo, D. Canone, D. Demarchi
{"title":"Long-Range Low-Power Soil Water Content Monitoring System for Precision Agriculture","authors":"Mattia Barezzi, U. Garlando, Francesca Pettiti, L. Nari, D. Gisolo, D. Canone, D. Demarchi","doi":"10.1109/LASCAS53948.2022.9789070","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789070","url":null,"abstract":"World population growth and desertification are increasing the food demand. Food production must increase to ensure food security in the following years. Smart agriculture tries to improve food production thanks to the adoption of electronic sensors to monitor and control fruit and vegetable crops. Another critical point in agriculture is the use of potable water. Precision irrigation strategies can be implemented to reduce water waste and increase crop production. This paper proposes a long-range, low-power sensor node to monitor soil water content. It is possible to place multiple sensor nodes in the field and use the gathered data to determine the most suitable irrigation strategy. The node communicates thanks to the LoRa protocol and it can also be used in remote areas where it is impossible to have an internet connection.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130418924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Highly Linear Large Signal Compact Voltage-to-Current Converter in 28 nm FD-SOI Technology 28nm FD-SOI技术的高线性大信号紧凑型电压-电流转换器
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789060
Andres Asprilla, A. Cathelin, Y. Deval
{"title":"Highly Linear Large Signal Compact Voltage-to-Current Converter in 28 nm FD-SOI Technology","authors":"Andres Asprilla, A. Cathelin, Y. Deval","doi":"10.1109/LASCAS53948.2022.9789060","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789060","url":null,"abstract":"This paper presents the design of a linear wide output range voltage-to-current (V2I) converter which has a constant transconductance value from a given input voltage. The proposed circuit offers a solution with a low footprint (33 $mu mathrm{m} mathrm{x} 24 mu mathrm{m})$, low power consumption (34 $mumathrm{W})$, and a transconductance variation less than 2%. In this paper, the output current is used to generate a pair of symmetrical voltages, equal in magnitude and opposite in sign, to provide the tuning of a body-controlled ring oscillator. The circuit has been designed and fabricated in 28 nm FD-SOI technology from STMicroelectronics.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128441733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Validation of a Signal Acquisition for Electrochemical Noise Corrosion Monitoring System 电化学噪声腐蚀监测系统信号采集的验证
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789082
Marco Antonio de Campos Menezes, T. Pimenta, C. B. Martinez
{"title":"Validation of a Signal Acquisition for Electrochemical Noise Corrosion Monitoring System","authors":"Marco Antonio de Campos Menezes, T. Pimenta, C. B. Martinez","doi":"10.1109/LASCAS53948.2022.9789082","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789082","url":null,"abstract":"Corrosion is a problem that can cause losses up to 4.5% of GDP in industrialized countries besides the environmental impacts. This study proposes a corrosion monitoring system using the passive technique based on electrochemical noise (EN). It measures the natural levels of a corrosion process signal (current or voltage) without any external artificial stimulation. It uses the Zero Resistance Ammeter (ZRA), which allows to galvanically couple two similar working electrodes and measure the current flow at the same time. This approach has the advantage of a simple setup, since there is no need of any signal injection or external stimulus. Due to dynamic and stochastic nature of the signal, this work considers numerical and graphic characteristics of two corrosion systems, carbon steel and stainless steel. The experiments were conducted repeatedly to obtain data for the analysis in time and frequency domains.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131618376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An NML in-plane Wire Crossing Structure 一种NML平面内导线交叉结构
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789062
L. O. Luz, J. Nacif, Ricardo S. Ferreira, O. V. Neto
{"title":"An NML in-plane Wire Crossing Structure","authors":"L. O. Luz, J. Nacif, Ricardo S. Ferreira, O. V. Neto","doi":"10.1109/LASCAS53948.2022.9789062","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789062","url":null,"abstract":"The Nanomagnetic Logic (NML) is a promising new technology to build low-power devices at room temperature. Furthermore, this technology allows mixing logic and memory on the same device, providing area and power consumption optimizations. However, when designing complex nanomagnetic circuits, we often need to cross wires without needing to include extra layers of interacting nanomagnets that would make the synthesis process more complex. In this work, we propose and analyze the behavior of a new structure that allows an in-plane wire crossing that can be useful in designing complex NML circuits. The design was built based on a clocking scheme of 4 phases and simulated using the Landauer-Lifshitz-Gilbert equation through the NMLSim v2 simulator. Our design can implement horizontal and vertical wire crossings without any extra time delay by exploring the time-division multiplexing method.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133982986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Technical and pedagogical challenges in micro-nanoelectronics for facing upcoming digital society 面对即将到来的数字社会，微纳电子学的技术和教学挑战
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789087
O. Bonnaud
{"title":"Technical and pedagogical challenges in micro-nanoelectronics for facing upcoming digital society","authors":"O. Bonnaud","doi":"10.1109/LASCAS53948.2022.9789087","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789087","url":null,"abstract":"The worldwide evolution towards a digital society is strongly underway, thanks in particular to the incredible increase in the performance of electronics and micro-nanoelectronics in all their compartments, from elementary components to circuits and systems. This accelerating evolution, especially in terms of data flow corresponding to the multiplication of connected objects, raises new challenges of two kinds: technical/technological and human. On the technical side, we need to reduce the size of systems and their energy consumption by controlling elementary devices and circuit architectures. On the human level, we need to adapt skills to the new technical and technological challenges and above all to increase the pool of talent due to the extremely rapid development of applications, despite the growing assistance provided by all the design and manufacturing assistance tools. After having developed the global context, this paper focuses on the different limitations and associated challenges and on the approach brought by the French microelectronics training network for the learning of the know-how in connection with the recovery plans dedicated to the electronics industry.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123948157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Low-Cost Cold Plasma Generator Circuits Designed for Laboratory Applications 设计用于实验室应用的低成本冷等离子体发生器电路
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789052
Sergio Diaz, J. Guzmán, C. Tenreiro, Roberto O. Ramírez, Oscar Hernandez
{"title":"A Low-Cost Cold Plasma Generator Circuits Designed for Laboratory Applications","authors":"Sergio Diaz, J. Guzmán, C. Tenreiro, Roberto O. Ramírez, Oscar Hernandez","doi":"10.1109/LASCAS53948.2022.9789052","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789052","url":null,"abstract":"The generation of cold plasma is applied to different processes as grinding of rocks, hardening of metals and sterilization of food. To obtain cold plasma in a vacuum chamber, it is necessary to partially ionize the gas between the electrodes, generating high voltage pulses of the order of microseconds. The repetition frequencies of these pulses depend on the specific application. The design of the power sources can include a synthetic pulse formation line (PFN) triggered or using vacuum valves or static converter arrays. In laboratory applications where applications for cold plasma are studied, it is convenient for safety to design automatized systems for plasma characterization. This work presents the design of a pulsating source and its attached measurements systems, presenting the procedures and auxiliary circuits for real time plasma characterization on a digital based system.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127891475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
VLSI Architecture Design Methodology for Deep learning based Upper Limb and Lower Limb Movement Classification for Rehabilitation Application 基于深度学习的上肢和下肢运动分类的VLSI体系结构设计方法
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS) Pub Date : 2022-03-01 DOI: 10.1109/LASCAS53948.2022.9789091
Anagha Nimbekar, Y. Dinesh, A. Gautam, Vidhumouli Hunsigida, Appa Rao Nali, A. Acharyya
{"title":"VLSI Architecture Design Methodology for Deep learning based Upper Limb and Lower Limb Movement Classification for Rehabilitation Application","authors":"Anagha Nimbekar, Y. Dinesh, A. Gautam, Vidhumouli Hunsigida, Appa Rao Nali, A. Acharyya","doi":"10.1109/LASCAS53948.2022.9789091","DOIUrl":"https://doi.org/10.1109/LASCAS53948.2022.9789091","url":null,"abstract":"Recently, many works have proposed an highly accurate deep learning based movement classification algorithms for the assistive technology applications. But very less importance is given for it's corresponding hardward implementation. In this paper we proposed an VLSI architecture design methodology for deep learning based movement classification for assistive technology applications. LoCoMo-Net and MyoNet are the two Deep learning based networks proposed by Gautam et al [1] [2] for upper limb and lower limb for assistive technology. The proposed architecture is capable enough to adapt both the networks. We have implemented the architecture on ZYNQ ultra-$text{scale} + text{MPSoC} text{zcu}102 text{FPGA}$. LoCoMo-Net consumes 3.5 Watts of on chip power and MyoNet consumes 5 Watts of on chip power on the FPGA. LoCoMo-Net takes 1.876ms of time to classify the task and MyoNet takes 61.988ms of time to classify the task on FPGA.","PeriodicalId":356481,"journal":{"name":"2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129146446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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