Ultra-Low-Power CMOS Voltage Reference Topologies Regarding Technology Node

Abstract

Ultra-low-power (ULP) designs have received great attention due to the emergence of a wide variety of devices of internet-of-things (IoT) applications. The scaling down of CMOS technology introduces additional challenges for designers, since circuit topologies are usually modified in order to maintain performance under the effects of the next technology. In this paper, a comparative study of ULP voltage references (VRs) is advanced considering four CMOS technologies: 180 nm (bulk), 90 nm (bulk), 65 nm (bulk) and 28 nm (FD-SOI). In addition, major nanometer effects such as drain induced barrier lowering (DIBL), gate induced drain leakage (GIDL), gate leakage due to direct tunneling, junction leakage, among others, are carefully considered in order to suggest an appropriated VR topology regarding each technology node.